Lines Matching +full:0 +full:xd0000000
8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
13 * registers mapped at 0xd0000000. If you have such a device you will
18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
36 memory@0 {
38 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
45 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
60 reg = <0x30>;
72 * pin being sampled at reset (bit 0 of SAR).
85 reg = <0x12100 0x100>;
86 clocks = <&coreclk 0>;
96 pinctrl-0 = <&ge0_rgmii_pins>;
103 pinctrl-0 = <&ge1_rgmii_pins>;
122 pinctrl-0 = <&sata1_pwr_pin>;
136 pinctrl-0 = <&sata2_pwr_pin>;
150 pinctrl-0 = <&sata3_pwr_pin>;
164 pinctrl-0 = <&sata4_pwr_pin>;
176 pcie@1,0 {
177 /* Port 0, Lane 0 */
185 pcie@5,0 {
186 /* Port 1, Lane 0 */
193 phy0: ethernet-phy@0 { /* Marvell 88E1512 */
194 reg = <0>;
272 flash@0 {
276 reg = <0>; /* Chip select 0 */
293 partition@0 { /* u-boot */
295 reg = <0x00000000 0x000d0000>; /* 832KB */
300 reg = <0x000d0000 0x002d0000>; /* 2880KB */
305 reg = <0x003a0000 0x00430000>; /* 4250KB */
310 reg = <0x007d0000 0x00010000>; /* 64KB */
315 reg = <0x007e0000 0x00010000>; /* 64KB */
320 reg = <0x007f0000 0x00010000>; /* 64KB */