Lines Matching full:clkc

6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
29 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
31 			clocks = <&clkc CLKID_CPUCLK>;
41 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
43 			clocks = <&clkc CLKID_CPUCLK>;
53 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
55 			clocks = <&clkc CLKID_CPUCLK>;
65 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
67 			clocks = <&clkc CLKID_CPUCLK>;
254 			compatible = "amlogic,meson8-ddr-clkc";
308 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
311 			assigned-clocks = <&clkc CLKID_MALI>;
322 	clocks = <&clkc CLKID_AIU_GLUE>,
323 		 <&clkc CLKID_I2S_OUT>,
324 		 <&clkc CLKID_AOCLK_GATE>,
325 		 <&clkc CLKID_CTS_AMCLK>,
326 		 <&clkc CLKID_MIXER_IFACE>,
327 		 <&clkc CLKID_IEC958>,
328 		 <&clkc CLKID_IEC958_GATE>,
329 		 <&clkc CLKID_CTS_MCLK_I958>,
330 		 <&clkc CLKID_CTS_I958>;
436 	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
604 	clocks = <&clkc CLKID_EFUSE>;
614 	clocks = <&clkc CLKID_ETH>;
626 	clkc: clock-controller {  label
627 		compatible = "amlogic,meson8-clkc";
638 		clocks = <&clkc CLKID_VPU>;
640 		assigned-clocks = <&clkc CLKID_VPU>;
646 	clocks = <&clkc CLKID_RNG0>;
651 	clocks = <&clkc CLKID_CLK81>;
655 	clocks = <&clkc CLKID_CLK81>;
659 	clocks = <&clkc CLKID_CLK81>;
684 		clocks = <&clkc CLKID_PERIPH>;
697 		clocks = <&clkc CLKID_PERIPH>;
716 	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
726 		 <&clkc CLKID_FCLK_DIV4>,
727 		 <&clkc CLKID_FCLK_DIV3>,
728 		 <&clkc CLKID_FCLK_DIV5>,
729 		 <&clkc CLKID_SDHC>;
742 	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
747 	clocks = <&clkc CLKID_CLK81>;
751 	clocks = <&xtal>, <&clkc CLKID_CLK81>;
757 	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
763 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
769 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
775 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
781 	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
787 	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
793 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
800 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;