Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
9 #include <dt-bindings/dma/sun4i-a10.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 osc24M: clk-24M {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <24000000>;
21 clock-output-names = "osc24M";
24 osc32k: clk-32k {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <32768>;
28 clock-output-names = "osc32k";
33 #address-cells = <1>;
34 #size-cells = <0>;
37 compatible = "arm,arm926ej-s";
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
49 sram-controller@1c00000 {
50 compatible = "allwinner,suniv-f1c100s-system-control",
51 "allwinner,sun4i-a10-system-control";
53 #address-cells = <1>;
54 #size-cells = <1>;
58 compatible = "mmio-sram";
60 #address-cells = <1>;
61 #size-cells = <1>;
64 otg_sram: sram-section@0 {
65 compatible = "allwinner,suniv-f1c100s-sram-d",
66 "allwinner,sun4i-a10-sram-d";
74 compatible = "allwinner,suniv-f1c100s-spi",
75 "allwinner,sun8i-h3-spi";
78 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
79 clock-names = "ahb", "mod";
80 resets = <&ccu RST_BUS_SPI0>;
82 num-cs = <1>;
83 #address-cells = <1>;
84 #size-cells = <0>;
88 compatible = "allwinner,suniv-f1c100s-spi",
89 "allwinner,sun8i-h3-spi";
92 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
93 clock-names = "ahb", "mod";
94 resets = <&ccu RST_BUS_SPI1>;
96 num-cs = <1>;
97 #address-cells = <1>;
98 #size-cells = <0>;
102 compatible = "allwinner,suniv-f1c100s-mmc",
103 "allwinner,sun7i-a20-mmc";
105 clocks = <&ccu CLK_BUS_MMC0>,
106 <&ccu CLK_MMC0>,
107 <&ccu CLK_MMC0_OUTPUT>,
108 <&ccu CLK_MMC0_SAMPLE>;
109 clock-names = "ahb", "mmc", "output", "sample";
110 resets = <&ccu RST_BUS_MMC0>;
111 reset-names = "ahb";
113 pinctrl-names = "default";
114 pinctrl-0 = <&mmc0_pins>;
116 #address-cells = <1>;
117 #size-cells = <0>;
121 compatible = "allwinner,suniv-f1c100s-mmc",
122 "allwinner,sun7i-a20-mmc";
124 clocks = <&ccu CLK_BUS_MMC1>,
125 <&ccu CLK_MMC1>,
126 <&ccu CLK_MMC1_OUTPUT>,
127 <&ccu CLK_MMC1_SAMPLE>;
128 clock-names = "ahb", "mmc", "output", "sample";
129 resets = <&ccu RST_BUS_MMC1>;
130 reset-names = "ahb";
133 #address-cells = <1>;
134 #size-cells = <0>;
138 compatible = "allwinner,suniv-f1c100s-musb";
140 clocks = <&ccu CLK_BUS_OTG>;
141 resets = <&ccu RST_BUS_OTG>;
143 interrupt-names = "mc";
145 phy-names = "usb";
152 compatible = "allwinner,suniv-f1c100s-usb-phy";
154 reg-names = "phy_ctrl";
155 clocks = <&ccu CLK_USB_PHY0>;
156 clock-names = "usb0_phy";
157 resets = <&ccu RST_USB_PHY0>;
158 reset-names = "usb0_reset";
159 #phy-cells = <1>;
163 dma: dma-controller@1c02000 {
164 compatible = "allwinner,suniv-f1c100s-dma";
167 clocks = <&ccu CLK_BUS_DMA>;
168 resets = <&ccu RST_BUS_DMA>;
169 #dma-cells = <2>;
172 ccu: clock@1c20000 { label
173 compatible = "allwinner,suniv-f1c100s-ccu";
176 clock-names = "hosc", "losc";
177 #clock-cells = <1>;
178 #reset-cells = <1>;
181 intc: interrupt-controller@1c20400 {
182 compatible = "allwinner,suniv-f1c100s-ic";
184 interrupt-controller;
185 #interrupt-cells = <1>;
189 compatible = "allwinner,suniv-f1c100s-pinctrl";
192 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
193 clock-names = "apb", "hosc", "losc";
194 gpio-controller;
195 interrupt-controller;
196 #interrupt-cells = <3>;
197 #gpio-cells = <3>;
199 mmc0_pins: mmc0-pins {
202 drive-strength = <30>;
205 /omit-if-no-ref/
206 i2c0_pd_pins: i2c0-pd-pins {
211 spi0_pc_pins: spi0-pc-pins {
216 uart0_pe_pins: uart0-pe-pins {
221 /omit-if-no-ref/
222 uart1_pa_pins: uart1-pa-pins {
229 compatible = "allwinner,suniv-f1c100s-i2c",
230 "allwinner,sun6i-a31-i2c";
233 clocks = <&ccu CLK_BUS_I2C0>;
234 resets = <&ccu RST_BUS_I2C0>;
235 #address-cells = <1>;
236 #size-cells = <0>;
241 compatible = "allwinner,suniv-f1c100s-i2c",
242 "allwinner,sun6i-a31-i2c";
245 clocks = <&ccu CLK_BUS_I2C1>;
246 resets = <&ccu RST_BUS_I2C1>;
247 #address-cells = <1>;
248 #size-cells = <0>;
253 compatible = "allwinner,suniv-f1c100s-i2c",
254 "allwinner,sun6i-a31-i2c";
257 clocks = <&ccu CLK_BUS_I2C2>;
258 resets = <&ccu RST_BUS_I2C2>;
259 #address-cells = <1>;
260 #size-cells = <0>;
265 compatible = "allwinner,suniv-f1c100s-timer";
272 compatible = "allwinner,suniv-f1c100s-wdt",
273 "allwinner,sun6i-a31-wdt";
280 compatible = "allwinner,suniv-f1c100s-pwm",
281 "allwinner,sun7i-a20-pwm";
284 #pwm-cells = <3>;
289 compatible = "allwinner,suniv-f1c100s-ir",
290 "allwinner,sun6i-a31-ir";
292 clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
293 clock-names = "apb", "ir";
294 resets = <&ccu RST_BUS_IR>;
300 compatible = "allwinner,suniv-f1c100s-lradc",
301 "allwinner,sun8i-a83t-r-lradc";
308 compatible = "snps,dw-apb-uart";
311 reg-shift = <2>;
312 reg-io-width = <4>;
313 clocks = <&ccu CLK_BUS_UART0>;
314 resets = <&ccu RST_BUS_UART0>;
319 compatible = "snps,dw-apb-uart";
322 reg-shift = <2>;
323 reg-io-width = <4>;
324 clocks = <&ccu CLK_BUS_UART1>;
325 resets = <&ccu RST_BUS_UART1>;
330 compatible = "snps,dw-apb-uart";
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 clocks = <&ccu CLK_BUS_UART2>;
336 resets = <&ccu RST_BUS_UART2>;
341 #sound-dai-cells = <0>;
342 compatible = "allwinner,suniv-f1c100s-codec";
345 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
346 clock-names = "apb", "codec";
349 dma-names = "rx", "tx";
350 resets = <&ccu RST_BUS_CODEC>;