Lines Matching +full:word +full:- +full:size
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
101 kputc #'-'
105 kputc #'-'
110 kputc #'-'
121 .macro dbgadtb, begin, size argument
134 kphex \size, 8 /* Size of appended DTB */
152 * The kernel build system appends the size of the
154 * in little-endian form.
159 add \tmp1, \tmp1, \res @ address of inflated image size
215 .word _magic_sig @ Magic numbers to help the loader
216 .word _magic_start @ absolute load/run zImage address
217 .word _magic_end @ zImage end address
218 .word 0x04030201 @ endianness flag
219 .word 0x45454545 @ another magic number to indicate
220 .word _magic_table @ additional data table
234 * Booting from Angel - need to enter SVC mode and disable
251 * be needed here - is there an Angel SWI call for this?
269 * different platforms - we have chosen 128MB to allow
319 * That means r4 < pc || r4 - 16k page directory > &_end.
351 mov r5, #0 @ init dtb size to 0
355 * r5 = appended dtb size (still unknown)
359 * r9 = size of decompressed image
382 /* Get the initial DTB size */
388 /* preserve 64-bit alignment */
425 * kernel size to compensate if that .bss size is larger
434 /* Get the current DTB size */
438 /* preserve 64-bit alignment */
452 * r9 = size of decompressed image
455 * r4 - 16k page directory >= r10 -> OK
456 * r4 + image length <= address of wont_overwrite -> OK
475 * Bump to the next 256-byte boundary with the size of
479 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
505 sub r9, r6, r5 @ size to copy
525 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
527 stmdb r9!, {r0 - r3, r10 - r12, lr}
552 * r5 = appended dtb size (0 if not present)
576 * Bump bss entries to _edata + dtb size
582 addhi r1, r1, r5 @ entry += dtb size
660 LC0: .word LC0 @ r1
661 .word __bss_start @ r2
662 .word _end @ r3
663 .word _got_start @ r11
664 .word _got_end @ ip
665 .size LC0, . - LC0
668 LC1: .word .L_user_stack_end - LC1 @ sp
669 .word _edata - LC1 @ r6
670 .size LC1, . - LC1
673 .word _end - restart + 16384 + 1024*1024
676 .long (input_data_end - 4) - .
687 * dcache_line_size - get the minimum D-cache line size from the CTR register
699 and \tmp, \tmp, #0xf @ cache line size encoding
700 mov \reg, #4 @ bytes per word
701 mov \reg, \reg, lsl \tmp @ actual cache line size
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
793 __setup_mmu: sub r3, r4, #16384 @ Page directory size
803 add r10, r9, #0x10000000 @ a reasonable RAM size
810 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
858 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
860 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
882 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
888 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
892 bic r6, r6, #1 << 31 @ 32-bit translation system
914 orr r0, r0, #0x1000 @ I-cache enable
925 mov r1, #-1
956 * On v7-M the processor id is located in the V7M_SCB_CPUID
958 * v7-M (if existant at all) we just return early here.
961 * use cp15 registers that are not implemented on v7-M.
979 * - CPU ID match
980 * - CPU ID mask
981 * - 'cache on' method instruction
982 * - 'cache off' method instruction
983 * - 'cache flush' method instruction
994 .word 0x41000000 @ old ARM ID
995 .word 0xff00f000
1003 .word 0x41007000 @ ARM7/710
1004 .word 0xfff8fe00
1012 .word 0x41807200 @ ARM720T (writethrough)
1013 .word 0xffffff00
1019 .word 0x41007400 @ ARM74x
1020 .word 0xff00ff00
1025 .word 0x41009400 @ ARM94x
1026 .word 0xff00ff00
1031 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1032 .word 0xff0ffff0
1037 .word 0x00007000 @ ARM7 IDs
1038 .word 0x0000f000
1048 .word 0x4401a100 @ sa110 / sa1100
1049 .word 0xffffffe0
1054 .word 0x6901b110 @ sa1110
1055 .word 0xfffffff0
1060 .word 0x56056900
1061 .word 0xffffff00 @ PXA9xx
1066 .word 0x56158000 @ PXA168
1067 .word 0xfffff000
1072 .word 0x56050000 @ Feroceon
1073 .word 0xff0f0000
1087 .word 0x66015261 @ FA526
1088 .word 0xff01fff1
1095 .word 0x00020000 @ ARMv4T
1096 .word 0x000f0000
1101 .word 0x00050000 @ ARMv5TE
1102 .word 0x000f0000
1107 .word 0x00060000 @ ARMv5TEJ
1108 .word 0x000f0000
1113 .word 0x0007b000 @ ARMv6
1114 .word 0x000ff000
1119 .word 0x000f0000 @ new CPU Id
1120 .word 0x000f0000
1125 .word 0 @ unrecognised type
1126 .word 0
1134 .size proc_types, . - proc_types
1137 * If you get a "non-constant expression in ".if" statement"
1142 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1143 .error "The size of one or more proc_types entries is wrong."
1165 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1166 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1270 dcache_line_size r1, r2 @ r1 := dcache min line size
1271 sub r2, r1, #1 @ r2 := line size mask
1272 bic r0, r0, r2 @ round down start to line size
1274 bic r11, r11, r2 @ round down end to line size
1299 mov r2, #64*1024 @ default: 32K dcache size (*2)
1300 mov r11, #32 @ default: 32 byte line size
1307 mov r2, r2, lsl r1 @ base dcache size *2
1309 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1313 mov r11, r11, lsl r3 @ cache line size in bytes
1346 .size phexbuf, . - phexbuf
1464 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1467 @ U-Boot might decide to enter the EFI stub in HYP mode
1521 mov r5, #0 @ appended DTB size
1525 0: .long .L_user_stack_end - .