Lines Matching +full:config +full:- +full:space
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
169 config ARM_HAS_GROUP_RELOCS
176 supported in LLD until version 14. The combined range is -/+ 256 MiB,
180 config ARM_DMA_USE_IOMMU
186 config ARM_DMA_IOMMU_ALIGNMENT
194 for larger buffers it just a waste of address space. Drivers which has
196 virtual space with just a few allocations.
205 config SYS_SUPPORTS_APM_EMULATION
208 config HAVE_TCM
212 config HAVE_PROC_CPU
215 config NO_IOPORT_MAP
218 config SBUS
221 config STACKTRACE_SUPPORT
225 config LOCKDEP_SUPPORT
229 config ARCH_HAS_ILOG2_U32
232 config ARCH_HAS_ILOG2_U64
235 config ARCH_HAS_BANDGAP
238 config FIX_EARLYCON_MEM
241 config GENERIC_HWEIGHT
245 config GENERIC_CALIBRATE_DELAY
249 config ARCH_MAY_HAVE_PC_FDC
252 config ARCH_SUPPORTS_UPROBES
255 config GENERIC_ISA_DMA
258 config FIQ
261 config ARCH_MTD_XIP
264 config ARM_PATCH_PHYS_VIRT
269 Patch phys-to-virt and virt-to-phys translation functions at
273 This can only be used with non-XIP MMU kernels where the base
280 config NEED_MACH_IO_H
287 config NEED_MACH_MEMORY_H
294 config PHYS_OFFSET
307 config GENERIC_BUG
311 config PGTABLE_LEVELS
318 config MMU
319 bool "MMU-based Paged Memory Management Support"
322 Select if you want MMU-based virtualised addressing space
325 config ARM_SINGLE_ARMV7M
331 config ARCH_MMAP_RND_BITS_MIN
334 config ARCH_MMAP_RND_BITS_MAX
339 config ARCH_MULTIPLATFORM
357 # This is sorted alphabetically by mach-* pathname. However, plat-*
359 # plat- suffix) or along side the corresponding mach-* source.
361 source "arch/arm/mach-actions/Kconfig"
363 source "arch/arm/mach-alpine/Kconfig"
365 source "arch/arm/mach-artpec/Kconfig"
367 source "arch/arm/mach-aspeed/Kconfig"
369 source "arch/arm/mach-at91/Kconfig"
371 source "arch/arm/mach-axxia/Kconfig"
373 source "arch/arm/mach-bcm/Kconfig"
375 source "arch/arm/mach-berlin/Kconfig"
377 source "arch/arm/mach-clps711x/Kconfig"
379 source "arch/arm/mach-davinci/Kconfig"
381 source "arch/arm/mach-digicolor/Kconfig"
383 source "arch/arm/mach-dove/Kconfig"
385 source "arch/arm/mach-ep93xx/Kconfig"
387 source "arch/arm/mach-exynos/Kconfig"
389 source "arch/arm/mach-footbridge/Kconfig"
391 source "arch/arm/mach-gemini/Kconfig"
393 source "arch/arm/mach-highbank/Kconfig"
395 source "arch/arm/mach-hisi/Kconfig"
397 source "arch/arm/mach-hpe/Kconfig"
399 source "arch/arm/mach-imx/Kconfig"
401 source "arch/arm/mach-ixp4xx/Kconfig"
403 source "arch/arm/mach-keystone/Kconfig"
405 source "arch/arm/mach-lpc32xx/Kconfig"
407 source "arch/arm/mach-mediatek/Kconfig"
409 source "arch/arm/mach-meson/Kconfig"
411 source "arch/arm/mach-milbeaut/Kconfig"
413 source "arch/arm/mach-mmp/Kconfig"
415 source "arch/arm/mach-mstar/Kconfig"
417 source "arch/arm/mach-mv78xx0/Kconfig"
419 source "arch/arm/mach-mvebu/Kconfig"
421 source "arch/arm/mach-mxs/Kconfig"
423 source "arch/arm/mach-nomadik/Kconfig"
425 source "arch/arm/mach-npcm/Kconfig"
427 source "arch/arm/mach-omap1/Kconfig"
429 source "arch/arm/mach-omap2/Kconfig"
431 source "arch/arm/mach-orion5x/Kconfig"
433 source "arch/arm/mach-pxa/Kconfig"
435 source "arch/arm/mach-qcom/Kconfig"
437 source "arch/arm/mach-realtek/Kconfig"
439 source "arch/arm/mach-rpc/Kconfig"
441 source "arch/arm/mach-rockchip/Kconfig"
443 source "arch/arm/mach-s3c/Kconfig"
445 source "arch/arm/mach-s5pv210/Kconfig"
447 source "arch/arm/mach-sa1100/Kconfig"
449 source "arch/arm/mach-shmobile/Kconfig"
451 source "arch/arm/mach-socfpga/Kconfig"
453 source "arch/arm/mach-spear/Kconfig"
455 source "arch/arm/mach-sti/Kconfig"
457 source "arch/arm/mach-stm32/Kconfig"
459 source "arch/arm/mach-sunxi/Kconfig"
461 source "arch/arm/mach-tegra/Kconfig"
463 source "arch/arm/mach-ux500/Kconfig"
465 source "arch/arm/mach-versatile/Kconfig"
467 source "arch/arm/mach-vt8500/Kconfig"
469 source "arch/arm/mach-zynq/Kconfig"
471 # ARMv7-M architecture
472 config ARCH_LPC18XX
480 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
483 config ARCH_MPS2
489 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
490 with a range of available cores like Cortex-M3/M4/M7.
496 config ARCH_ACORN
499 config PLAT_ORION
505 config PLAT_ORION_LEGACY
509 config PLAT_VERSATILE
514 config IWMMXT
523 source "arch/arm/Kconfig-nommu"
526 config PJ4B_ERRATA_4742
540 config ARM_ERRATA_326103
541 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
544 Executing a SWP instruction to read-only memory does not set bit 11
549 config ARM_ERRATA_411920
558 config ARM_ERRATA_430973
562 This option enables the workaround for the 430973 Cortex-A8
565 same virtual address, whether due to self-modifying code or virtual
566 to physical address re-mapping, Cortex-A8 does not recover from the
567 stale interworking branch prediction. This results in Cortex-A8
572 available in non-secure mode.
574 config ARM_ERRATA_458693
579 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
586 register may not be available in non-secure mode and thus is not
590 config ARM_ERRATA_460075
595 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
599 workaround disables the write-allocate mode for the L2 cache via the
601 may not be available in non-secure mode and thus is not available on
605 config ARM_ERRATA_742230
610 This option enables the workaround for the 742230 Cortex-A9
614 the diagnostic register of the Cortex-A9 which causes the DMB
617 register may not be available in non-secure mode and thus is not
621 config ARM_ERRATA_742231
626 This option enables the workaround for the 742231 Cortex-A9
628 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
633 register of the Cortex-A9 which reduces the linefill issuing
635 diagnostics register may not be available in non-secure mode and thus
639 config ARM_ERRATA_643719
644 This option enables the workaround for the 643719 Cortex-A9 (prior to
650 config ARM_ERRATA_720789
654 This option enables the workaround for the 720789 Cortex-A9 (prior to
662 config ARM_ERRATA_743622
667 This option enables the workaround for the 743622 Cortex-A9
669 optimisation in the Cortex-A9 Store Buffer may lead to data
671 register of the Cortex-A9 which disables the Store Buffer
675 may not be available in non-secure mode and thus is not available on a
678 config ARM_ERRATA_751472
683 This option enables the workaround for the 751472 Cortex-A9 (prior
689 not be available in non-secure mode and thus is not available on
693 config ARM_ERRATA_754322
697 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
700 can populate the micro-TLB with a stale entry which may be hit with
704 config ARM_ERRATA_754327
708 This option enables the workaround for the 754327 Cortex-A9 (prior to
715 config ARM_ERRATA_364296
716 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
721 hit-under-miss enabled). It sets the undocumented bit 31 in
723 register, thus disabling hit-under-miss without putting the
727 config ARM_ERRATA_764369
732 affecting Cortex-A9 MPCore with two or more processors (all
741 config ARM_ERRATA_764319
745 This option enables the workaround for the 764319 Cortex-A9 erratum.
752 config ARM_ERRATA_775420
756 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
762 config ARM_ERRATA_798181
763 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
766 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
772 config ARM_ERRATA_773022
776 This option enables the workaround for the 773022 Cortex-A15
781 config ARM_ERRATA_818325_852422
786 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
788 - Cortex-A12 852422: Execution of a sequence of instructions might
790 any Cortex-A12 cores yet.
795 config ARM_ERRATA_821420
799 This option enables the workaround for the 821420 Cortex-A12
803 deadlock when the VMOV instructions are issued out-of-order.
805 config ARM_ERRATA_825619
809 This option enables the workaround for the 825619 Cortex-A12
812 and Device/Strongly-Ordered loads and stores might cause deadlock
814 config ARM_ERRATA_857271
818 This option enables the workaround for the 857271 Cortex-A12
822 config ARM_ERRATA_852421
826 This option enables the workaround for the 852421 Cortex-A17
831 config ARM_ERRATA_852423
836 - Cortex-A17 852423: Execution of a sequence of instructions might
838 any Cortex-A17 cores yet.
839 This is identical to Cortex-A12 erratum 852422. It is a separate
840 config option from the A12 erratum due to the way errata are checked
843 config ARM_ERRATA_857272
847 This option enables the workaround for the 857272 Cortex-A17 erratum.
849 This is identical to Cortex-A12 erratum 857271. It is a separate
850 config option from the A12 erratum due to the way errata are checked
859 config ISA
869 config ISA_DMA_API
872 config ARM_ERRATA_814220
881 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
888 config HAVE_SMP
891 This option should be selected by machines which have an SMP-
894 The only effect of this option is to make the SMP-related
897 config SMP
898 bool "Symmetric Multi-Processing"
908 If you say N here, the kernel will run on uni- and multiprocessor
914 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
915 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
916 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
920 config SMP_ON_UP
925 SMP kernels contain instructions which fail on non-SMP processors.
927 these instructions safe. Disabling it allows about 1K of space
933 config CURRENT_POINTER_IN_TPIDRURO
937 config IRQSTACKS
942 config ARM_CPU_TOPOLOGY
951 config SCHED_MC
952 bool "Multi-core scheduler support"
955 Multi-core scheduler support improves the CPU scheduler's decision
956 making when dealing with multi-core CPU chips at a cost of slightly
959 config SCHED_SMT
967 config HAVE_ARM_SCU
972 config HAVE_ARM_ARCH_TIMER
979 config HAVE_ARM_TWD
984 config MCPM
985 bool "Multi-Cluster Power Management"
989 for (multi-)cluster based systems, such as big.LITTLE based
992 config MCPM_QUAD_CLUSTER
1001 config BIG_LITTLE
1009 config BL_SWITCHER
1018 config BL_SWITCHER_DUMMY_IF
1036 config VMSPLIT_3G
1038 config VMSPLIT_3G_OPT
1041 config VMSPLIT_2G
1043 config VMSPLIT_1G
1047 config PAGE_OFFSET
1055 config KASAN_SHADOW_OFFSET
1064 config NR_CPUS
1065 int "Maximum number of CPUs (2-32)"
1073 debugging is enabled, which uses half of the per-CPU fixmap
1076 config HOTPLUG_CPU
1077 bool "Support for hot-pluggable CPUs"
1084 config ARM_PSCI
1090 implementing the PSCI specification for CPU-centric power
1095 config HZ_FIXED
1104 config HZ_100
1107 config HZ_200
1110 config HZ_250
1113 config HZ_300
1116 config HZ_500
1119 config HZ_1000
1124 config HZ
1134 config SCHED_HRTICK
1137 config THUMB2_KERNEL
1138 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1144 Thumb-2 mode.
1148 config ARM_PATCH_IDIV
1166 config AEABI
1173 space environment that is also compiled with EABI.
1183 config OABI_COMPAT
1198 If you know you'll be using only pure EABI user space then you
1204 config ARCH_SELECT_MEMORY_MODEL
1207 config ARCH_FLATMEM_ENABLE
1210 config ARCH_SPARSEMEM_ENABLE
1214 config HIGHMEM
1220 The address space of ARM processors is only 4 Gigabytes large
1221 and it has to accommodate user address space, kernel address
1222 space as well as some memory mapped IO. That means that, if you
1228 vmalloc space and actual amount of RAM, you may not need this
1233 config HIGHPTE
1234 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1242 user-space 2nd level page tables to reside in high memory.
1244 config ARM_PAN
1245 bool "Enable privileged no-access"
1251 use-after-free bugs becoming an exploitable privilege escalation
1258 config CPU_SW_DOMAIN_PAN
1262 Enable use of CPU domains to implement privileged no-access.
1264 CPUs with low-vector mappings use a best-efforts implementation.
1268 config CPU_TTBR0_PAN
1272 Enable privileged no-access by disabling TTBR0 page table walks when
1275 config HW_PERF_EVENTS
1279 config ARM_MODULE_PLTS
1294 Disabling this is usually safe for small single-platform
1297 config ARCH_FORCE_MAX_ORDER
1312 config ALIGNMENT_TRAP
1318 address divisible by 4. On 32-bit ARM processors, these non-aligned
1321 correct operation of some network protocols. With an IP-only
1324 config UACCESS_WITH_MEMCPY
1330 cores where a 8-word STM instruction give significantly higher
1334 between threads sharing the same address space if they invoke
1337 However, if the CPU data cache is using a write-allocate mode,
1340 config PARAVIRT
1347 config PARAVIRT_TIME_ACCOUNTING
1358 config XEN_DOM0
1362 config XEN
1376 config CC_HAVE_STACKPROTECTOR_TLS
1377 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1379 config STACKPROTECTOR_PER_TASK
1389 kernel's address space are forced to use the same canary value for
1399 config USE_OF
1406 config ARCH_WANT_FLAT_DTB_INSTALL
1409 config ATAGS
1418 config DEPRECATED_PARAM_STRUCT
1426 # TEXT and BSS so we preserve their values in the config files.
1427 config ZBOOT_ROM_TEXT
1431 The physical address at which the ROM-able zImage is to be
1433 ROM-able zImage formats normally set this to a suitable
1438 config ZBOOT_ROM_BSS
1443 for the ROM-able zImage which must be available while the
1446 Platforms which normally make use of ROM-able zImage formats
1451 config ZBOOT_ROM
1459 config ARM_APPENDED_DTB
1479 config ARM_ATAG_DTB_COMPAT
1496 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1499 Uses the command-line options passed by the boot loader instead of
1503 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1506 The command-line arguments provided by the boot loader will be
1511 config CMDLINE
1517 architectures, you should supply some command-line options at build
1526 config CMDLINE_FROM_BOOTLOADER
1529 Uses the command-line options passed by the boot loader. If
1533 config CMDLINE_EXTEND
1536 The command-line arguments provided by the boot loader will be
1539 config CMDLINE_FORCE
1545 command-line options your boot loader passes to the kernel.
1548 config XIP_KERNEL
1549 bool "Kernel Execute-In-Place from ROM"
1553 Execute-In-Place allows the kernel to run from non-volatile storage
1555 space since the text section of the kernel is not loaded from flash
1556 to RAM. Read-write sections, such as the data section and stack,
1558 it has to run directly from flash, so it will take more space to
1570 config XIP_PHYS_ADDR
1579 config XIP_DEFLATED_DATA
1587 copied, saving some precious ROM space. A possible drawback is a
1590 config ARCH_SUPPORTS_KEXEC
1593 config ATAGS_PROC
1601 config ARCH_SUPPORTS_CRASH_DUMP
1604 config ARCH_DEFAULT_CRASH_DUMP
1607 config AUTO_ZRELADDR
1613 will be determined at run-time, either by masking the current IP
1618 config EFI_STUB
1621 config EFI
1631 by UEFI firmware (such as non-volatile variables, realtime
1637 config DMI
1646 continue to boot on existing non-UEFI platforms.
1652 to be enabled much earlier than we do on ARM, which is non-trivial.
1668 config FPE_NWFPE
1675 your machine has an FPA or floating point co-processor podule.
1680 config FPE_NWFPE_XP
1684 Say Y to include 80-bit support in the kernel floating-point
1685 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1686 Note that gcc does not generate 80-bit operations by default,
1692 config FPE_FASTFPE
1699 It is very simple, and approximately 3-6 times faster than NWFPE.
1706 config VFP
1707 bool "VFP-format floating point maths"
1713 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1718 config VFPv3
1723 config NEON
1730 config KERNEL_MODE_NEON
1742 config ARCH_SUSPEND_POSSIBLE
1747 config ARM_CPU_SUSPEND
1751 config ARCH_HIBERNATION_POSSIBLE