Lines Matching +full:pins +full:- +full:are +full:- +full:numbered

1 // SPDX-License-Identifier: GPL-2.0
40 	int ofs = (irq - 16) / 8;  in cabriolet_update_irq_hw()
47 	cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));  in cabriolet_enable_irq()
53 	cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);  in cabriolet_disable_irq()
78 		pld &= pld - 1;	/* clear least bit set */  in cabriolet_device_interrupt()
111 	if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL))  in common_init_irq()
112 		pr_err("Failed to register isa-cascade interrupt\n");  in common_init_irq()
162  * the on-board NCR and Tulip chips.  In the code below, I have used
166  * that's printed on the board.  The interrupt pins from the PCI slots
167  * are wired into 3 interrupt summary registers at 0x804, 0x805 and
170  * In the table, -1 means don't assign an IRQ number.  This is usually
181 		{  -1,   -1,   -1,    -1,    -1},  /* IdSel 8,  SIO         */  in eb66p_map_irq()
192  * are numbered differently.  In the code below, I have used slot
196  * printed on the board.  The interrupt pins from the PCI slots are
200  * In the table, -1 means don't assign an IRQ number.  This is usually
212 		{   -1,   -1,   -1,    -1,    -1}, /* IdSel 8,  SIO         */  in cabriolet_map_irq()
222 	if (pc873xx_probe() == -1) {  in cabriolet_enable_ide()
246  * register and cleared by writing a "0". There are 3 mask registers
258  * ISA     +--------------------------------------------------------------+
262  *         +--------------------------------------------------------------+
264  *         +--------------------------------------------------------------+
266  *         +--------------------------------------------------------------+
268  *         Note: The mask register is write-only.
289 		{   -1,   -1,   -1,    -1,    -1},  /* IdSel  8, SIO */  in alphapc164_map_irq()