Lines Matching +full:1 +full:- +full:1024
1 /* SPDX-License-Identifier: GPL-2.0 */
15 * may also have PCI-PCI bridges present, and then we'd configure the
38 * that get passed through the PCI<->ISA bridge chip. Although this causes
39 * us to set the PCI->Mem window bases lower than normal, we still allocate
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
53 #define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024)
61 #define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
62 #define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024)
68 #define DEFAULT_MEM_BASE ((128+16)*1024*1024)
71 #define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
73 #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
75 #define DEFAULT_AGP_APER_SIZE (64*1024*1024)
79 * later) adheres to the PCI-PCI bridge specification. This says that
107 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
108 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
116 /* The following macro is used to implement the table-based irq mapping
117 function for all single-bus Alphas. */
120 ({ long _ctl_ = -1; \
122 _ctl_ = irq_tab[slot - min_idsel][pin]; \
128 /* ??? The 8400 has a 32-byte pte entry, and the entire table apparently
131 a bit further. Probably with per-bus operation tables. */