Lines Matching +full:0 +full:x220
16 inb(0x0229); in es1888_init()
17 inb(0x0229); in es1888_init()
18 inb(0x0229); in es1888_init()
19 inb(0x022b); in es1888_init()
20 inb(0x0229); in es1888_init()
21 inb(0x022b); in es1888_init()
22 inb(0x0229); in es1888_init()
23 inb(0x0229); in es1888_init()
24 inb(0x022b); in es1888_init()
25 inb(0x0229); in es1888_init()
26 inb(0x0220); /* This sets the base address to 0x220 */ in es1888_init()
29 outb(0x01, 0x0226); /* reset */ in es1888_init()
30 inb(0x0226); /* pause */ in es1888_init()
31 outb(0x00, 0x0226); /* release reset */ in es1888_init()
32 while (!(inb(0x022e) & 0x80)) /* wait for bit 7 to assert*/ in es1888_init()
34 inb(0x022a); /* pause */ in es1888_init()
35 outb(0xc6, 0x022c); /* enable extended mode */ in es1888_init()
36 inb(0x022a); /* pause, also forces the write */ in es1888_init()
37 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ in es1888_init()
39 outb(0xb1, 0x022c); /* setup for write to Interrupt CR */ in es1888_init()
40 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ in es1888_init()
42 outb(0x14, 0x022c); /* set IRQ 5 */ in es1888_init()
43 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ in es1888_init()
45 outb(0xb2, 0x022c); /* setup for write to DMA CR */ in es1888_init()
46 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ in es1888_init()
48 outb(0x18, 0x022c); /* set DMA channel 1 */ in es1888_init()
49 inb(0x022c); /* force the write */ in es1888_init()