Lines Matching full:vip
46 #define vip volatile int * macro
116 stat0 = *(vip)CIA_IOC_CIA_ERR; in conf_read()
117 *(vip)CIA_IOC_CIA_ERR = stat0; in conf_read()
119 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ in conf_read()
123 cia_cfg = *(vip)CIA_IOC_CFG; in conf_read()
124 *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; in conf_read()
126 *(vip)CIA_IOC_CFG; in conf_read()
136 value = *(vip)addr; in conf_read()
149 *(vip)CIA_IOC_CFG = cia_cfg; in conf_read()
151 *(vip)CIA_IOC_CFG; in conf_read()
170 stat0 = *(vip)CIA_IOC_CIA_ERR; in conf_write()
171 *(vip)CIA_IOC_CIA_ERR = stat0; in conf_write()
173 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ in conf_write()
177 cia_cfg = *(vip)CIA_IOC_CFG; in conf_write()
178 *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; in conf_write()
180 *(vip)CIA_IOC_CFG; in conf_write()
190 *(vip)addr = value; in conf_write()
192 *(vip)addr; /* read back to force the write */ in conf_write()
199 *(vip)CIA_IOC_CFG = cia_cfg; in conf_write()
201 *(vip)CIA_IOC_CFG; in conf_write()
260 *(vip)CIA_IOC_PCI_TBIA = 3; /* Flush all locked and unlocked. */ in cia_pci_tbi()
262 *(vip)CIA_IOC_PCI_TBIA; in cia_pci_tbi()
292 ctrl = *(vip)CIA_IOC_CIA_CTRL; in cia_pci_tbi_try2()
293 *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; in cia_pci_tbi_try2()
295 *(vip)CIA_IOC_CIA_CTRL; in cia_pci_tbi_try2()
321 *(vip)CIA_IOC_CIA_CTRL = ctrl; in cia_pci_tbi_try2()
323 *(vip)CIA_IOC_CIA_CTRL; in cia_pci_tbi_try2()
340 *(vip)CIA_IOC_PCI_Wn_BASE(window) = CIA_BROKEN_TBIA_BASE | 3; in cia_prepare_tbia_workaround()
341 *(vip)CIA_IOC_PCI_Wn_MASK(window) in cia_prepare_tbia_workaround()
343 *(vip)CIA_IOC_PCI_Tn_BASE(window) = virt_to_phys(ppte) >> 2; in cia_prepare_tbia_workaround()
364 ctrl = *(vip)CIA_IOC_CIA_CTRL; in verify_tb_operation()
365 *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; in verify_tb_operation()
367 *(vip)CIA_IOC_CIA_CTRL; in verify_tb_operation()
376 *(vip)CIA_IOC_TB_TAGn(0) = tag0; in verify_tb_operation()
377 *(vip)CIA_IOC_TB_TAGn(1) = 0; in verify_tb_operation()
378 *(vip)CIA_IOC_TB_TAGn(2) = 0; in verify_tb_operation()
379 *(vip)CIA_IOC_TB_TAGn(3) = 0; in verify_tb_operation()
380 *(vip)CIA_IOC_TB_TAGn(4) = 0; in verify_tb_operation()
381 *(vip)CIA_IOC_TB_TAGn(5) = 0; in verify_tb_operation()
382 *(vip)CIA_IOC_TB_TAGn(6) = 0; in verify_tb_operation()
383 *(vip)CIA_IOC_TB_TAGn(7) = 0; in verify_tb_operation()
384 *(vip)CIA_IOC_TBn_PAGEm(0,0) = pte0; in verify_tb_operation()
385 *(vip)CIA_IOC_TBn_PAGEm(0,1) = 0; in verify_tb_operation()
386 *(vip)CIA_IOC_TBn_PAGEm(0,2) = 0; in verify_tb_operation()
387 *(vip)CIA_IOC_TBn_PAGEm(0,3) = 0; in verify_tb_operation()
401 temp = *(vip)CIA_IOC_TB_TAGn(0); in verify_tb_operation()
407 temp = *(vip)CIA_IOC_TB_TAGn(1); in verify_tb_operation()
413 temp = *(vip)CIA_IOC_TBn_PAGEm(0,0); in verify_tb_operation()
447 temp = *(vip)CIA_IOC_TB_TAGn(0); in verify_tb_operation()
529 *(vip)CIA_IOC_TB_TAGn(0) = 2; in verify_tb_operation()
530 *(vip)CIA_IOC_TB_TAGn(1) = 2; in verify_tb_operation()
531 *(vip)CIA_IOC_TB_TAGn(2) = 2; in verify_tb_operation()
532 *(vip)CIA_IOC_TB_TAGn(3) = 2; in verify_tb_operation()
544 *(vip)CIA_IOC_CIA_CTRL = ctrl; in verify_tb_operation()
546 *(vip)CIA_IOC_CIA_CTRL; in verify_tb_operation()
552 *(vip)CIA_IOC_PCI_W0_BASE = 0; in verify_tb_operation()
553 *(vip)CIA_IOC_PCI_W1_BASE = 0; in verify_tb_operation()
582 saved_config.err_mask = *(vip)CIA_IOC_ERR_MASK; in cia_save_srm_settings()
583 saved_config.cia_ctrl = *(vip)CIA_IOC_CIA_CTRL; in cia_save_srm_settings()
584 saved_config.hae_mem = *(vip)CIA_IOC_HAE_MEM; in cia_save_srm_settings()
585 saved_config.hae_io = *(vip)CIA_IOC_HAE_IO; in cia_save_srm_settings()
586 saved_config.pci_dac_offset = *(vip)CIA_IOC_PCI_W_DAC; in cia_save_srm_settings()
589 saved_config.cia_cnfg = *(vip)CIA_IOC_CIA_CNFG; in cia_save_srm_settings()
595 saved_config.window[i].w_base = *(vip)CIA_IOC_PCI_Wn_BASE(i); in cia_save_srm_settings()
596 saved_config.window[i].w_mask = *(vip)CIA_IOC_PCI_Wn_MASK(i); in cia_save_srm_settings()
597 saved_config.window[i].t_base = *(vip)CIA_IOC_PCI_Tn_BASE(i); in cia_save_srm_settings()
608 *(vip)CIA_IOC_PCI_Wn_BASE(i) = saved_config.window[i].w_base; in cia_restore_srm_settings()
609 *(vip)CIA_IOC_PCI_Wn_MASK(i) = saved_config.window[i].w_mask; in cia_restore_srm_settings()
610 *(vip)CIA_IOC_PCI_Tn_BASE(i) = saved_config.window[i].t_base; in cia_restore_srm_settings()
613 *(vip)CIA_IOC_HAE_MEM = saved_config.hae_mem; in cia_restore_srm_settings()
614 *(vip)CIA_IOC_HAE_IO = saved_config.hae_io; in cia_restore_srm_settings()
615 *(vip)CIA_IOC_PCI_W_DAC = saved_config.pci_dac_offset; in cia_restore_srm_settings()
616 *(vip)CIA_IOC_ERR_MASK = saved_config.err_mask; in cia_restore_srm_settings()
617 *(vip)CIA_IOC_CIA_CTRL = saved_config.cia_ctrl; in cia_restore_srm_settings()
620 *(vip)CIA_IOC_CIA_CNFG = saved_config.cia_cnfg; in cia_restore_srm_settings()
636 cia_rev = *(vip)CIA_IOC_CIA_REV & CIA_REV_MASK; in do_init_arch()
644 temp = *(vip)CIA_IOC_ERR_MASK; in do_init_arch()
647 *(vip)CIA_IOC_ERR_MASK = temp; in do_init_arch()
650 temp = *(vip)CIA_IOC_CIA_ERR; in do_init_arch()
651 *(vip)CIA_IOC_CIA_ERR = temp; in do_init_arch()
654 temp = *(vip)CIA_IOC_CIA_CTRL; in do_init_arch()
656 *(vip)CIA_IOC_CIA_CTRL = temp; in do_init_arch()
661 *(vip)CIA_IOC_CFG = 0; in do_init_arch()
664 *(vip)CIA_IOC_HAE_MEM = 0; in do_init_arch()
665 *(vip)CIA_IOC_HAE_IO = 0; in do_init_arch()
671 temp = *(vip)CIA_IOC_CIA_CNFG; in do_init_arch()
673 *(vip)CIA_IOC_CIA_CNFG = temp; in do_init_arch()
678 *(vip)CIA_IOC_CIA_REV; in do_init_arch()
732 *(vip)CIA_IOC_PCI_W0_BASE = hose->sg_isa->dma_base | 3; in do_init_arch()
733 *(vip)CIA_IOC_PCI_W0_MASK = (hose->sg_isa->size - 1) & 0xfff00000; in do_init_arch()
734 *(vip)CIA_IOC_PCI_T0_BASE = virt_to_phys(hose->sg_isa->ptes) >> 2; in do_init_arch()
736 *(vip)CIA_IOC_PCI_W2_BASE = __direct_map_base | 1; in do_init_arch()
737 *(vip)CIA_IOC_PCI_W2_MASK = (__direct_map_size - 1) & 0xfff00000; in do_init_arch()
738 *(vip)CIA_IOC_PCI_T2_BASE = 0 >> 2; in do_init_arch()
756 *(vip)CIA_IOC_PCI_W3_BASE = 0; in do_init_arch()
758 *(vip)CIA_IOC_PCI_W1_BASE = 0; in do_init_arch()
761 *(vip)CIA_IOC_PCI_W3_BASE = 0; in do_init_arch()
763 *(vip)CIA_IOC_PCI_W3_BASE = 0x00000000 | 1 | 8; in do_init_arch()
764 *(vip)CIA_IOC_PCI_W3_MASK = 0xfff00000; in do_init_arch()
765 *(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2; in do_init_arch()
768 *(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32; in do_init_arch()
826 jd = *(vip)CIA_IOC_CIA_ERR; in cia_pci_clr_err()
827 *(vip)CIA_IOC_CIA_ERR = jd; in cia_pci_clr_err()
829 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write. */ in cia_pci_clr_err()
869 tmp = *(vip)CIA_IOC_PCI_W_DAC & 0xFFUL; in cia_decode_pci_error()