Lines Matching +full:pcie +full:- +full:root +full:- +full:port +full:- +full:1
1 .. SPDX-License-Identifier: GPL-2.0
4 HiSilicon PCIe Tune and Trace device
10 HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
12 to dynamically monitor and tune the PCIe link's events (tune),
15 PCIe link's performance.
17 On Kunpeng 930 SoC, the PCIe Root Complex is composed of several
18 PCIe cores. Each PCIe core includes several Root Ports and a PTT
20 tracing the links of the PCIe core.
23 +--------------Core 0-------+
25 | | [Root Port]---[Endpoint]
26 | | [Root Port]---[Endpoint]
27 | | [Root Port]---[Endpoint]
28 Root Complex |------Core 1-------+
30 | | [Root Port]---[ Switch ]---[Endpoint]
31 | | [Root Port]---[Endpoint] `-[Endpoint]
32 | | [Root Port]---[Endpoint]
33 +---------------------------+
39 IO dies (SICL, Super I/O Cluster), where there's one PCIe Root
48 PTT tune is designed for monitoring and adjusting PCIe link parameters (events).
50 covers the PCIe core to which the PTT device belongs.
62 1
70 1. Tx Path QoS Control
71 ------------------------
74 the PCIe core.
76 - qos_tx_cpl: weight of Tx completion TLPs
77 - qos_tx_np: weight of Tx non-posted TLPs
78 - qos_tx_p: weight of Tx posted TLPs
80 The weight influences the proportion of certain packets on the PCIe link.
85 The available tune data of these events is [0, 1, 2].
91 -------------------------
93 Following files are provided to tune the buffer of tx path of the PCIe core.
95 - rx_alloc_buf_level: watermark of Rx requested
96 - tx_alloc_buf_level: watermark of Tx requested
105 The available tune data of above events is [0, 1, 2].
114 can be used to analyze the transactions and usage condition of the PCIe
116 or those downstream of a set of Root Ports on the same core of the PTT
127 $ perf record -e hisi_ptt0_2/filter=0x80001,type=1,direction=1,
128 format=1/ -- sleep 5
130 This will trace the TLP headers downstream root port 0000:00:10.1 (event
134 1. Filter
135 ---------
137 The TLP headers to trace can be filtered by the Root Ports or the Requester ID
141 1 for Root Port filter and 0 for Requester filter. Bit[15:0] indicates the
142 filter value. The value for a Root Port is a mask of the core port id which is
144 is the Requester ID (Device ID of the PCIe function). Bit[18:16] is currently
148 value will be 0x00101. If the desired filter is Root Port 0000:00:10.0 then
151 The driver also presents every supported Root Port and Requester filter through
152 sysfs. Each filter will be an individual file with name of its related PCIe
153 device name (domain:bus:device.function). The files of Root Port filters are
157 Note that multiple Root Ports can be specified at one time, but only one
158 Endpoint function can be specified in one trace. Specifying both Root Port
167 -------
173 - 8'b00000001: posted requests (P)
174 - 8'b00000010: non-posted requests (NP)
175 - 8'b00000100: completions (CPL)
181 ------------
184 to the Root Port or the PCIe core, by specifying the `direction` parameter.
189 - 4'b0000: inbound TLPs (P, NP, CPL)
190 - 4'b0001: outbound TLPs (P, NP, CPL)
191 - 4'b0010: outbound TLPs (P, NP, CPL) and inbound TLPs (P, NP, CPL B)
192 - 4'b0011: outbound TLPs (P, NP, CPL) and inbound TLPs (CPL A)
197 - 4'b0000: reserved
198 - 4'b0001: outbound TLPs (P, NP, CPL)
199 - 4'b0010: inbound TLPs (P, NP, CPL B)
200 - 4'b0011: inbound TLPs (CPL A)
204 - completion A (CPL A): completion of CHI/DMA/Native non-posted requests, except for CPL B
205 - completion B (CPL B): completion of DMA remote2local and P2P non-posted requests
208 --------------
214 - 4'b0000: 4DW length per TLP header
215 - 4'b0001: 8DW length per TLP header
217 The traced TLP header format is different from the PCIe standard.
220 (Header DW0-3 shown below). For example, the TLP header for Memory
221 Reads with 64-bit addresses is shown in PCIe r5.0, Figure 2-17;
225 possibly a prefix for a PASID TLP prefix (see Figure 6-20, PCIe r5.0).
233 |---------------------------------------|-------------------|
245 timestamp. DW1-DW3 of the trace buffer entry contain DW1-DW3
252 |-----|---------|---|---|---|---|-------------|-------------|
259 --------------------
267 +->[DMA addr 0]->[DMA addr 1]->[DMA addr 2]->[DMA addr 3]-+
268 +---------------------------------------------------------+
275 adjust the size by specifying the `-m` parameter of the perf command.
278 -----------
280 You can decode the traced data with `perf report -D` command (currently
289 . 00000008: 0f 1e 00 01 Header DW1
295 . 00000028: 0f 1e 00 01 Header DW1
301 . 00000048: 0f 1e 00 01 Header DW1