Lines Matching +full:rx +full:- +full:sync +full:- +full:clock

15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
52 to synchronise the link while the Tx and Rx lines are used to transmit and
53 receive the audio data. Bit clock usually varies depending on sample rate
54 while sync runs at the sample rate. PCM also supports Time Division
58 Common PCM operating modes:-
61   MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
64   MSB is transmitted on rising edge of FRAME/SYNC.