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1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
30 exposing a low pin count Serial Peripheral Interface (SPI) to the host
32 to existing low-end microcontrollers which do not integrate a MAC
36 --------
38 The MAC-PHY is specified to carry both data (Ethernet frames) and control
39 (register access) transactions over a single full-duplex serial peripheral
43 -----------------
47 read/write transfers. A chunk is the basic element of data transactions
54 low to the MAC-PHY and ends with the deassertion of CSn high. In between
64 Each transmit data chunk begins with a 32-bit data header followed by a
70 chunk consists of a data chunk payload ending with a 32-bit data footer.
76 ---------
78 10BASE-T1x MAC-PHY Serial Interface Specification,
80 Link: https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.p…
83 ---------------------
85 .. code-block:: none
87 +----------+ +-------------------------------------+
88 | | | MAC-PHY |
89 | |<---->| +-----------+ +-------+ +-------+ |
91 | | | +-----------+ +-------+ +-------+ |
92 +----------+ +-------------------------------------+
95 ---------------------
97 .. code-block:: none
99 +----------------------------------------------------------+
101 +----------------------------------------------------------+
106 +----------------------+ +-----------------------------+
107 | MAC Driver |<--->| OPEN Alliance TC6 Framework |
108 +----------------------+ +-----------------------------+
113 +----------------------------------------------------------+
115 +----------------------------------------------------------+
120 +----------------------------------------------------------+
121 | 10BASE-T1x MAC-PHY Device |
122 +----------------------------------------------------------+
125 --------------
130 - Probed by SPI subsystem.
132 - Initializes OA TC6 framework for the MAC-PHY.
134 - Registers and configures the network device.
136 - Sends the tx ethernet frames from n/w subsystem to OA TC6 framework.
141 - Initializes PHYLIB interface.
143 - Registers mac-phy interrupt.
145 - Performs mac-phy register read/write operation using the control
146 transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY
149 - Performs Ethernet frames transaction using the data transaction protocol
150 for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY
153 - Forwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w
160 the MAC-PHY will be converted into multiple transmit data chunks. Each
161 transmit data chunk will have a 4 bytes header which contains the
165 .. code-block:: none
167 +---------------------------------------------------+
169 | +---------------------------+ +----------------+ | MOSI
170 | | 64 bytes chunk payload | | 4 bytes header | |------------>
171 | +---------------------------+ +----------------+ |
172 +---------------------------------------------------+
176 DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
177 transaction. For TX data chunks, this bit shall be ’1’.
178 0 - Control command
179 1 - Data chunk
181 SEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an
182 even/odd transmit data chunk sequence to the MAC-PHY.
184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
185 the MAC-PHY from conveying RX data on the MISO for the
191 RSVD (Bit 28..24) - Reserved: All reserved bits shall be ‘0’.
193 VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
194 If the MAC-PHY does not implement these bits, the host
197 DV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate
199 (DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the
201 the setting of the DV bit in the data header.
203 SV (Bit 20) - Start Valid flag. The SPI host shall set this bit when the
205 transmit data chunk payload. Otherwise, this bit shall be
206 zero. This bit is not to be confused with the Start-of-Frame
209 SWO (Bit 19..16) - Start Word Offset. When SV = 1, this field shall
210 contain the 32-bit word offset into the transmit data
211 chunk payload that points to the start of a new
215 RSVD (Bit 15) - Reserved: All reserved bits shall be ‘0’.
217 EV (Bit 14) - End Valid flag. The SPI host shall set this bit when the end
219 chunk payload. Otherwise, this bit shall be zero.
221 EBO (Bit 13..8) - End Byte Offset. When EV = 1, this field shall contain
226 TSC (Bit 7..6) - Timestamp Capture. Request a timestamp capture when the
228 00 - Do not capture a timestamp
229 01 - Capture timestamp into timestamp capture register A
230 10 - Capture timestamp into timestamp capture register B
231 11 - Capture timestamp into timestamp capture register C
233 RSVD (Bit 5..1) - Reserved: All reserved bits shall be ‘0’.
235 P (Bit 0) - Parity. Parity bit calculated over the transmit data header.
238 The number of buffers available in the MAC-PHY to store the incoming
240 available transmit credits in the MAC-PHY can be read either from the
242 received from the MAC-PHY. The SPI host should not write more data chunks
248 chunks, the MAC-PHY interrupt is asserted to SPI host. On reception of the
253 The Ethernet frames that are typically transferred from MAC-PHY to SPI
259 .. code-block:: none
261 +---------------------------------------------------+
263 | +----------------+ +---------------------------+ | MISO
264 | | 4 bytes footer | | 64 bytes chunk payload | |------------>
265 | +----------------+ +---------------------------+ |
266 +---------------------------------------------------+
270 EXST (Bit 31) - Extended Status. This bit is set when any bit in the
273 HDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHY
274 received a control or data header with a parity error.
276 SYNC (Bit 29) - Configuration Synchronized flag. This bit reflects the
277 state of the SYNC bit in the CONFIG0 configuration
278 register (see Table 12). A zero indicates that the MAC-PHY
284 RCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to
289 pending in the MAC-PHY’s buffer for reading.
291 VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
292 If not implemented, the MAC-PHY shall set these bits to
295 DV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicate
300 SV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the current
302 Otherwise, this bit is zero. The SV bit is not to be
303 confused with the Start-of-Frame Delimiter (SFD) byte
306 SWO (Bit 19..16) - Start Word Offset. When SV = 1, this field contains the
307 32-bit word offset into the receive data chunk payload
308 containing the first byte of a new received Ethernet
309 frame. When a receive timestamp has been added to the
314 FD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC has
315 detected a condition for which the SPI host should drop the
316 received Ethernet frame. This bit is only valid at the end
317 of a received Ethernet frame (EV = 1) and shall be zero at
320 EV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of a
324 EBO (Bit 13..8) - End Byte Offset: When EV = 1, this field contains the
329 RTSA (Bit 7) - Receive Timestamp Added. This bit is set when a 32-bit or
330 64-bit timestamp has been added to the beginning of the
331 received Ethernet frame. The MAC-PHY shall set this bit to
334 RTSP (Bit 6) - Receive Timestamp Parity. Parity bit calculated over the
335 32-bit/64-bit timestamp added to the beginning of the
337 MAC-PHY shall set this bit to zero when RTSA = 0.
339 TXC (Bit 5..1) - Transmit Credits. This field contains the minimum number
341 can write in a single transaction without incurring a
344 P (Bit 0) - Parity. Parity bit calculated over the receive data footer.
348 chunks available in the MAC-PHY which is provided in the receive chunk
349 footer (RCA - Receive Chunks Available). SPI host will create data invalid
351 case there are valid Ethernet frames to transmit to the MAC-PHY. The
352 receive chunks available in MAC-PHY can be read either from the Buffer
357 MAC-PHY interrupt is asserted to SPI host. On reception of the first data
361 MAC-PHY Interrupt
364 The MAC-PHY interrupt is asserted when the following conditions are met.
366 Receive chunks available - This interrupt is asserted when the previous
371 Transmit chunk credits available - This interrupt is asserted when the
376 Extended status event - This interrupt is asserted when the previous data
387 DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
388 transaction. For control commands, this bit shall be ‘0’.
389 0 - Control command
390 1 - Data chunk
392 HDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicates
393 that a header was received with a parity error. The SPI
394 host should always clear this bit. The MAC-PHY ignores the
397 WNR (Bit 29) - Write-Not-Read. This bit indicates if data is to be written
401 AID (Bit 28) - Address Increment Disable. When clear, the address will be
402 automatically post-incremented by one following each
407 MMS (Bit 27..24) - Memory Map Selector. This field selects the specific
410 ADDR (Bit 23..8) - Address. Address of the first register within the
413 LEN (Bit 7..1) - Length. Specifies the number of registers to read/write.
416 or written starting at the address specified in ADDR. A
417 length of zero shall read or write a single register.
419 P (Bit 0) - Parity. Parity bit calculated over the control command header.
424 MAC-PHY. Each control commands are composed of a 4 bytes control command
427 The MAC-PHY ignores the final 4 bytes of data from the SPI host at the end
429 from the MAC-PHY back to the SPI host to identify which register write
433 write data. Control write commands can write either a single register or
435 written, the address is automatically post-incremented by the MAC-PHY.
439 The MAC-PHY ignores all data from the SPI host following the control
441 command is also echoed from the MAC-PHY back to the SPI host to identify
445 by register read data. Control read commands can read either a single
447 registers are read, the address is automatically post-incremented by the
448 MAC-PHY. Reading any unimplemented or undefined registers shall return
468 Write a single register in the MAC-PHY.
473 Writing multiple consecutive registers starting from @address in the MAC-PHY.
479 Read a single register in the MAC-PHY.
484 Reading multiple consecutive registers starting from @address in the MAC-PHY.
491 the MAC-PHY.
496 frames data to start at the beginning of any receive data chunk payload with a