Lines Matching full:dependency
55 - Address-dependency barriers (historical).
189 There is an obvious address dependency here, as the value loaded into D depends
394 address-dependency barriers; see the "SMP barrier pairing" subsection.
397 (2) Address-dependency barriers (historical).
404 An address-dependency barrier is a weaker form of read barrier. In the
407 the second load will be directed), an address-dependency barrier would
411 An address-dependency barrier is a partial ordering on interdependent
417 considered can then perceive. An address-dependency barrier issued by
422 the address-dependency barrier.
427 [!] Note that the first load really has to have an _address_ dependency and
428 not a control dependency. If the address for the second load is dependent
429 on the first load, but the dependency is through a conditional rather than
430 actually loading the address itself, then it's a _control_ dependency and
434 [!] Note that address-dependency barriers should normally be paired with
438 dependency barriers. Nowadays, APIs for marking loads from shared
440 address-dependency barriers.
444 A read barrier is an address-dependency barrier plus a guarantee that all
452 Read memory barriers imply address-dependency barriers, and so can
561 ADDRESS-DEPENDENCY BARRIERS (HISTORICAL)
574 address-dependency barriers.
577 load-to-store relations, address-dependency barriers are not necessary
580 The requirement of address-dependency barriers is a little subtle, and
594 doesn't imply an address-dependency barrier.
596 There's a clear address dependency here, and it would seem that by the end of
611 To deal with this, READ_ONCE() provides an implicit address-dependency barrier
621 <implicit address-dependency barrier>
638 An address-dependency barrier is not required to order dependent writes
655 Therefore, no address-dependency barrier is required to order the read into
657 even without an implicit address-dependency barrier of modern READ_ONCE():
662 of dependency ordering is to -prevent- writes to the data structure, along
668 Note well that the ordering provided by an address dependency is local to
673 The address-dependency barrier is very important to the RCU system,
687 A load-load control dependency requires a full read memory barrier, not
688 simply an (implicit) address-dependency barrier to make it work correctly.
692 <implicit address-dependency barrier>
694 /* BUG: No address dependency!!! */
699 dependency, but rather a control dependency that the CPU may short-circuit
845 defeating control dependency:
881 A weakly ordered CPU would have no dependency of any sort between the load
889 Note well that the ordering provided by a control dependency is local
909 destroy the control dependency while respecting the letter of the
920 dependency into nonexistence. Careful use of READ_ONCE() or
921 atomic{,64}_read() can help to preserve your control dependency.
925 of the if-statement containing the control dependency, including
928 control dependency.
949 with an address-dependency barrier, a control dependency, an acquire barrier,
951 read barrier, control dependency, or an address-dependency barrier pairs
970 <implicit address-dependency barrier>
980 <implicit control dependency>
990 match the loads after the read barrier or the address-dependency barrier, and
1043 Secondly, address-dependency barriers act as partial orderings on address-
1089 If, however, an address-dependency barrier were to be placed between the load
1100 <address-dependency barrier>
1314 Placing a read barrier or an address-dependency barrier just before the second
1416 only the data dependency shown below:
1422 <data dependency> <read barrier>
1429 The key point is that although CPU 2's data dependency orders its load
1845 ADDRESS DEPENDENCY READ_ONCE()
1848 All memory barriers except the address-dependency barriers imply a compiler
2462 CPU, that CPU's dependency ordering logic will take care of everything else.
2912 the address-dependency barrier really becomes necessary as this synchronises