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2 Kernel driver i2c-piix4
8 Datasheet: Publicly available at the Intel website
9 * ServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
10 Datasheet: Only available via NDA from ServerWorks
12 Datasheet: Not publicly available
16 Datasheet: Publicly available at the AMD website
18 * AMD Hudson-2, ML, CZ
19 Datasheet: Not publicly available
21 Datasheet: Not publicly available
23 Datasheet: Publicly available at the SMSC website http://www.smsc.com
26 - Frodo Looijaard <[email protected]>
27 - Philip Edelbrock <[email protected]>
31 -----------------
40 -----------
45 SMBus - you can not access it on I2C levels. The good news is that it
47 timing problems. The bad news is that non-SMBus devices connected to it can
50 Do ``lspci -v`` and see whether it contains an entry like this::
80 The AMD SB700, SB800, SP5100 and Hudson-2 chipsets implement two
81 PIIX4-compatible SMBus controllers. If your BIOS initializes the
90 00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
92 for all possible PCI ids (and ``lspci -n`` to match them). Let's assume the
93 device is located at 00:0f.0.
94 2) Now you just need to change the value in 0xD2 register. Get it first with
95 command: ``lspci -xxx -s 00:0f.0``
96 If the value is 0x3 then you need to change it to 0x1:
97 ``setpci -s 00:0f.0 d2.b=1``
103 Hardware-specific issues
104 ------------------------
115 ----------------------------
120 $ i2cdetect -l
122 i2c-7 unknown SMBus PIIX4 adapter port 0 at 0b00 N/A
123 i2c-8 unknown SMBus PIIX4 adapter port 2 at 0b00 N/A
124 i2c-9 unknown SMBus PIIX4 adapter port 1 at 0b20 N/A
132 Name (_ADR, 0x00140000)
135 Name (_ADR, 0)
152 driver to the 0x1C device on the I2C bus created by the PIIX port 0::
159 0x001c,
164 0
169 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
171 Package () { "compatible", Package() { "jedec,jc-42.4-temp" } },