Lines Matching +full:msi +full:- +full:base +full:- +full:spi
1 .. SPDX-License-Identifier: GPL-2.0
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
22 Unlike other common SPI/I2C controllers, THC handles the HID device data interrupt and reset
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
37 | +-----------------------------------+ |
39 | +-----------------------------------+ |
40 | +-----------------------------------+ |
41 | | HID Multi-touch Driver | |
42 | +-----------------------------------+ |
43 | +-----------------------------------+ |
45 | +-----------------------------------+ |
46 | +-----------------------------------+ |
48 | +-----------------------------------+ |
49 | +-----------------------------------+ |
51 | +-----------------------------------+ |
52 | +----------------+ +----------------+ |
54 | +----------------+ +----------------+ |
55 ----------------------------------------------
56 ----------------------------------------------
57 | +-----------------------------------+ |
59 | +-----------------------------------+ |
60 | +-----------------------------------+ |
62 | +-----------------------------------+ |
63 | +-----------------------------------+ |
65 | +-----------------------------------+ |
66 ----------------------------------------------
70 reports over the SPI/I2C bus to the THC Controller on the host.
79 low-level driver that manages the THC Controller and implements HIDSPI/HIDI2C protocol.
83 ------------------------
86 ---------------------------------
88 | +---------------------------+ |
90 | +---------------------------+ |
91 | +---------------------------+ |
93 | +---------------------------+ |
94 +---------------+ | +------------+ +------------+ |
95 | System Memory +---+--+ DMA | | PIO | |
96 +---------------+ | +------------+ +------------+ |
97 | +---------------------------+ |
99 | +---------------------------+ |
100 | +------------+ +------------+ |
101 | | SPI/I2C | | GPIO | |
103 | +------------+ +------------+ |
104 ---------------------------------
111 PIO (Programmed I/O, defined in section 3.2) status and control, SPI bus configure, I2C subIP
119 SPI bus and I2C bus to finish a bus data transaction, it also can automatically handle
125 As THC supports HIDSPI/HIDI2C protocols, it has SPI controller and I2C subIP in it to expose
126 SPI bus and I2C bus. THC also integrates a GPIO controller to provide interrupt line support
133 ------------------
141 --------------------
143 THC supports two types of bus for Touch IC connection: Enhanced SPI bus and I2C bus.
145 2.2.1 SPI Port
148 When PORT_TYPE = 00b in MMIO registers, THC uses SPI interfaces to communicate with external
149 Touch IC. THC enhanced SPI Bus supports different SPI modes: standard Single IO mode,
159 Beside IO mode, driver also needs to configure SPI bus speed. THC supports up to 42MHz SPI clock
162 For THC sending data to Touch IC, the data flow on SPI bus::
164 | --------------------THC sends---------------------------------|
167 For THC receiving data from Touch IC, the data flow on SPI bus::
169 | ---------THC Sends---------------||-----Touch IC sends--------|
176 is configured to I2C mode. Comparing to SPI mode which can be configured through MMIO registers
195 ----------
200 When THC is configured to SPI mode, opcodes are used for determining the read/write IO mode.
201 There are some OPCode examples for SPI IO mode:
204 opcode Corresponding SPI command
223 Here are the THC pre-defined opcodes for I2C mode:
228 0x12 Read I2C SubIP APB internal registers 0h - FFh
229 0x13 Write I2C SubIP APB internal registers 0h - FFh
236 -------
240 I/O operations, driver should pre-program PIO control registers and PIO data registers and kick
262 - Program read/write data size in THC_SS_BC.
263 - Program I/O target address in THC_SW_SEQ_DATA0_ADDR.
264 - If write, program the write data in THC_SW_SEQ_DATA0..THC_SW_SEQ_DATAn.
265 - Program the PIO opcode in THC_SS_CMD.
266 - Set TSSGO = 1 to start the PIO write sequence.
267 - If THC_SS_CD_IE = 1, SW will receives a MSI when the PIO is completed.
268 - If read, read out the data in THC_SW_SEQ_DATA0..THC_SW_SEQ_DATAn.
271 -------
283 software, THC will start auto-handling receiving logic.
285 For SPI mode, THC RxDMA sequence is: when Touch IC triggers a interrupt to THC, THC reads out
289 RxDMA PRD table read pointer, then trigger a MSI interrupt to notify driver RxDMA finishing
296 input report data. After that, THC update RxDMA PRD table read pointer, then trigger a MSI interrupt
328 -------
344 ------------------------ -------------- --------------
345 | PRD table base address +----+ PRD table #1 +-----+ PRD Entry #1 |
346 ------------------------ -------------- --------------
347 --------------
349 --------------
350 --------------
352 --------------
360 To simplify the design, SW assumes worst-case memory fragmentation. Therefore,each PRD table shall
362 number of PRD-entries per PRD table.
419 .. code-block:: c
437 --------------
439 - Call ACPI _RST method to reset Touch IC device.
440 - Read the reset response from TIC through PIO read.
441 - Issue a command to retrieve device descriptor from Touch IC through PIO write.
442 - Read the device descriptor from Touch IC through PIO read.
443 - If the device descriptor is valid, allocate DMA buffers and configure all DMA channels.
444 - Issue a command to retrieve report descriptor from Touch IC through DMA.
447 --------------------------
451 - Touch IC interrupts the THC Controller using an in-band THC interrupt.
452 - THC Sequencer reads the input report header by transmitting read approval as a signal
454 - THC Sequencer executes a Input Report Body Read operation corresponding to the value
456 - THC DMA engine begins fetching data from the THC Sequencer and writes to host memory
460 - The THC Sequencer checks for the “Last Fragment Flag” bit in the Input Report Header.
462 - If the “Last Fragment Flag” bit is enabled the THC Sequencer enters End-of-Frame Processing.
466 - THC DMA engine increments the read pointer of the Read PRD CB, sets EOF interrupt status
468 - If THC EOF interrupt is enabled by the driver in the control register (THC_M_PRT_READ_DMA_CNTRL_2…
473 - THC QuickSPI driver checks CB write Ptr and CB read Ptr to identify if any data frame in DMA
475 - THC QuickSPI driver gets first unprocessed PRD table.
476 - THC QuickSPI driver scans all PRD entries in this PRD table to calculate the total frame size.
477 - THC QuickSPI driver copies all frame data out.
478 - THC QuickSPI driver checks the data type according to input report body, and calls related
480 - THC QuickSPI driver updates write Ptr.
483 ---------------------------
487 - HID core calls raw_request callback with a request to THC QuickSPI driver.
488 - THC QuickSPI Driver converts request provided data into the output report packet and copies it
490 - Start TxDMA to complete the write operation.
496 --------------
498 - Read device descriptor from Touch IC device through PIO write followed by read.
499 - If the device descriptor is valid, allocate DMA buffers and configure all DMA channels.
500 - Use PIO or TxDMA to write a SET_POWER request to TIC's command register, and check if the
502 - Use PIO or TxDMA to write a RESET request to TIC's command register. If the write operation
504 - Use SWDMA to read report descriptor through TIC's report descriptor register.
507 --------------------------
511 - Touch IC asserts the interrupt indicating that it has an interrupt to send to HOST.
514 - THC Sequencer continues the Read operation as per the size of data indicated in the
516 - THC DMA engine begins fetching data from the THC Sequencer and writes to host memory
521 - THC Sequencer enters End-of-Input Report Processing.
522 - If the device has no more input reports to send to the host, it de-asserts the interrupt
528 - THC DMA engine increments the read pointer of the Read PRD CB, sets EOF interrupt status
530 - If THC EOF interrupt is enabled by the driver in the control register
535 - THC QuickI2C driver checks CB write Ptr and CB read Ptr to identify if any data frame in DMA
537 - THC QuickI2C driver gets first unprocessed PRD table.
538 - THC QuickI2C driver scans all PRD entries in this PRD table to calculate the total frame size.
539 - THC QuickI2C driver copies all frame data out.
540 - THC QuickI2C driver call hid_input_report to send the input report content to HID core, which
543 - THC QuickI2C driver updates write Ptr.
546 ---------------------------
550 - HID core call THC QuickI2C raw_request callback.
551 - THC QuickI2C uses PIO or TXDMA to write a SET_REPORT request to TIC's command register. Report
553 - THC QuickI2C programs TxDMA buffer with TX Data to be written to TIC's data register. The first
567 - HIDSPI: https://download.microsoft.com/download/c/a/0/ca07aef3-3e10-4022-b1e9-c98cea99465d/HidSpi…
568 - HIDI2C: https://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-ov…