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7 interact with each other. On this page, the focus is shifted to the display
8 code architecture. Hence, it is reasonable to remind the reader that the code
10 abstractions and operations to connect different APIs with the hardware
12 to access and configure DCN/DCE hardware (DCE is also part of DC, but for
16    For this page, we will use the term GPU to refers to dGPU and APU.
21 From the display hardware perspective, it is plausible to expect that if a
22 problem is well-defined, it will probably be implemented at the hardware level.
24 a very well-defined scope, the solution is usually implemented as a policy at
31 necessary to use some of these instances. The core has policies in place for
34 actions. When the state changes from A to B, the transition is considered
35 easier to maneuver if the hardware resource is still used for the same set of
36 driver objects. Usually, adding and removing a resource to a `pipe_ctx` (more
37 details below) is not a problem; however, moving a resource from one `pipe_ctx`
38 to another should be avoided.
43 footprint is more desirable, but it has many associated challenges.
44 Unfortunately, there is no straight-forward analytic way to determine if a
45 configuration is the best one for the context due to the enormous variety of
46 variables related to this problem (e.g., many different DCN/DCE hardware
49 is possible to support it or not. This type of policy is extremely complex to
50 create and maintain, and amdgpu driver relies on Display Mode Library (DML) to
54 determine policies to manage them. All of the above information is conveyed to
56 driver's perspective. This page hopes to allow the reader to better navigate
65 .. kernel-figure:: dc-components.svg
67 The first layer of the diagram is the high-level DC API represented by the
72 API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
78 -------------
81 attention to the names in the boxes since they represent a data structure in
84 .. kernel-figure:: dc-arch-overview.svg
87 initialized per GPU; for example, one GPU has one `dc` instance, two GPUs have
88 two `dc` instances, and so forth. In other words we have one 'dc' per 'amdgpu'
92 is a low-level abstraction for the connector. One interesting aspect of the
94 platform/board and not by the SoC. The `dc_link` struct is the high-level data
103    conections like eDP or cases where the output is connected to other devices.
108 overview which is `dc_stream` and `dc_state`. The `dc_stream` stores many
110 represents the data flow from the connector to the display. Next we have
113 version of `drm_crtc` and represents the post-blending pipeline.
116 think about it as an abstraction similar to `drm_plane` that represents the
117 pre-blending portion of the pipeline. This image was probably processed by GFX
118 and is ready to be composited under a `dc_stream`. Normally, the driver may
119 have one or more `dc_plane` connected to the same `dc_stream`, which defines a
123 ----------------
125 Now that we have covered the basic objects, it is time to examine some of the
129 preparing for enabling other parts of the API. It is important to highlight
134 struct. Its main function is to put the hardware in a valid state. It is worth
136 a requirement to put it in a valid state; this function has multiple callbacks
137 for the hardware-specific initialization, whereas `dc_hardware_init` does the
144 initialized, it is useful to figure out if any of them are already connected to
146 out if any display is connected to the device, the challenging phase starts:
147 configuring the monitor to show something. Nonetheless, dealing with the ideal
150 commits. The only interface DC provides to the configuration phase is the
153 important to add that even if the display supports some specific configuration,
157 phase starts. This task activates one or more `dc_stream` at this phase, and in
158 the best-case scenario, you might be able to turn the display on with a black
160 associated with it). The final step would be to call the