Lines Matching +full:pixel +full:- +full:combiner

12 .. kernel-figure:: dc_pipeline_overview.svg
21 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
22   processing such as color space conversion, linearization of pixel data, tone
26   multiple planes, using global or per-pixel alpha.
28 * **Output Pixel Processing (OPP)**: Process and format pixels to be sent to
31 * **Output Pipe Timing Combiner (OPTC)**: It generates time output to combine
40 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
45   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
68 1. Pixel data interface (red): Represents the pixel data flow;
86 ----------------------
102 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
104 is to change, blend and compose pixel data, while BE's job is to frame a
105 generic pixel stream to a specific display's pixel stream.
108 ---------
110 Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel
112 different pixel formats and outputs them to DPP in uniform streams through 4
116 representation and convert them to a DCN specific floating-point format (i.e.,
117 different from the IEEE floating-point format). In the process, CNVC also
118 applies a degamma function to transform the data from non-linear to linear
119 space to relax the floating-point calculations following. Data would stay in
120 this floating-point format from DPP to OPP.
125 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
130 ---------------------
144 .. kernel-figure:: pipeline_4k_no_split.svg
147 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
148 this log can help us to see part of this pipeline behavior in real-time::
166 .. kernel-figure:: pipeline_4k_split.svg
189 -----------
196 in order to support outputs that need a very high pixel clock, or for
205 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
217 Since DCN hardware is double-buffered the DC driver is able to program the
222 .. kernel-figure:: global_sync_vblank.svg
228 updates, i.e. it allows for multiple re-configurations between VUpdate
232 .. kernel-figure:: config_example.svg