Lines Matching +full:buffered +full:- +full:negative

12 .. kernel-figure:: dc_pipeline_overview.svg
21 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
26   multiple planes, using global or per-pixel alpha.
40 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
45   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
86 ----------------------
102 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
108 ---------
116 representation and convert them to a DCN specific floating-point format (i.e.,
117 different from the IEEE floating-point format). In the process, CNVC also
118 applies a degamma function to transform the data from non-linear to linear
119 space to relax the floating-point calculations following. Data would stay in
120 this floating-point format from DPP to OPP.
125 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
130 ---------------------
144 .. kernel-figure:: pipeline_4k_no_split.svg
147 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
148 this log can help us to see part of this pipeline behavior in real-time::
166 .. kernel-figure:: pipeline_4k_split.svg
189 -----------
191 Many DCN registers are double buffered, most importantly the surface address.
205 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
213 atomically programmed (i.e. double buffered) registers. Even though it is
217 Since DCN hardware is double-buffered the DC driver is able to program the
222 .. kernel-figure:: global_sync_vblank.svg
225 to a number of negative consequences, most of them quite catastrophic.
228 updates, i.e. it allows for multiple re-configurations between VUpdate
232 .. kernel-figure:: config_example.svg