Lines Matching +full:system +full:- +full:firmware
1 .. SPDX-License-Identifier: GPL-2.0
14 Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and
15 Processing System (PSYS). IPU6 are visible on the PCI bus as a single device, it
26 The IPU6 is connecting to the system fabric with Buttress which is enabling host
27 driver to control the IPU6, it also allows IPU6 access the system memory to
30 Buttress mainly manages several system functionalities: power management,
31 interrupt handling, firmware authentication and global timer sync.
34 ------------------------
51 ---------
60 Security and firmware authentication
61 -------------------------------------
63 To address the IPU6 firmware security concerns, the IPU6 firmware needs to
67 authenticating the IPU6 firmware. The authenticated firmware binary is copied
68 into an isolated memory region. Firmware authentication process is implemented
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
82 calibrate the timestamp based on the timestamp in response event from firmware.
89 The IPU6 has its own scalar processor where the firmware run at and an internal
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
91 allow that scalar processors to access the internal memory and external system
93 levels of page lookup tables stored in system memory which are maintained by the
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
101 Firmware file format
104 The IPU6 firmware is in Code Partition Directory (CPD) file format. The CPD
105 firmware contains a CPD header, several CPD entries and components. The CPD
106 component includes 3 entries - manifest, metadata and module data. Manifest and
108 specific to IPU6 which holds the binary data of firmware called package
109 directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
110 the CPD firmware file and gets the package directory binary data of the IPU6
111 firmware, copies it to specific DMA buffer and sets its base address to Buttress
113 firmware binary.
119 The IPU6 driver communicates with firmware via the Syscom ABI. Syscom is an
120 inter-processor communication mechanism between the IPU scalar processors and
121 the CPU. There are a number of resources shared between firmware and software.
122 A system memory region where the message queues reside, firmware can access the
125 registers where the queue read and write indices reside. Software and firmware
131 initiating and starting the communication with firmware. Firmware and software
132 must use same configurations. The IPU6 Buttress has a number of firmware boot
134 initialise the Syscom state, then driver can request firmware to start and run via
137 Input System
140 IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can
141 capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
143 D-PHYs and CSI-2 ports lane mapping
144 -----------------------------------
146 The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
147 Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL
148 D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
149 adaptional layer between D-PHY and CSI-2 receiver controller which includes port
150 configuration, PHY wrapper or private test interfaces for D-PHY. There are 3
151 D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
152 ``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.
154 Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
155 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
156 see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
157 Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
158 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
159 lanes so IPU6 support maximum 6 CSI-2 ports.
161 .. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
162 lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
163 maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
164 port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
165 data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
166 will not be available as the 4 data lanes are shared by CSI-2 port 0
169 ISYS firmware ABIs
170 ------------------
172 The IPU6 firmware implements a series of ABIs for software access. In general,
174 ipu6_fw_isys_stream_cfg_data_abi`` and sends the configuration to firmware via
181 Once the driver gets the interrupt from firmware that indicates stream open
183 command to request firmware to start capturing image frames. ``STREAM_CAPTURE``
184 command queues the buffers to firmware with ``struct
186 response from firmware, ``PIN_DATA_READY`` means a buffer is ready on a specific