Lines Matching +full:in +full:- +full:line
18 line is not general purpose, it is not GPIO and should not be handled by a
19 GPIO chip. The use case is the indicative: certain lines in a system may be
21 of a general purpose I/O. On the other hand a LED driver line may be used as a
26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
31 use hardware offsets 0..31 for these, corresponding to bits 0..31 in the
35 line is never made visible outside of the driver.
37 On top of this internal number, each GPIO line also needs to have a global
38 number in the integer GPIO namespace so that it can be used with the legacy GPIO
40 assigned), and for each GPIO line the global number will be (base + hardware
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
55 In the gpiolib framework each GPIO controller is packaged as a "struct
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
63 - method to return the IRQ number associated to a given GPIO line
64 - flag saying whether calls to its methods may sleep
65 - optional line names array to identify lines
66 - optional debugfs dump method (showing extra state information)
67 - optional base number (will be automatically assigned if omitted)
68 - optional label for diagnostics and GPIO chip mapping using platform data
75 Often a gpio_chip is part of an instance-specific structure with states not
77 Chips such as audio codecs will have complex non-GPIO states.
81 NULL or the label associated with that GPIO line when it was requested.
84 sleepable APIs (like PM runtime) in its gpio_chip implementation (.get/.set
91 -----------------------------
96 - Debouncing
97 - Single-ended modes (open drain/open source)
98 - Pull up and pull down resistor enablement
105 which will result in pinctrl_gpio_set_config() being called and eventually
106 ending up in the pin control back-end "behind" the GPIO controller, usually
110 If a pin controller back-end is used, the GPIO controller or hardware
111 description needs to provide "GPIO ranges" mapping the GPIO line offsets to pin
112 numbers on the pin controller so they can properly cross-reference each other.
116 --------------------------------
120 line is pulled high/low quickly at very short intervals for mechanical
121 reasons. This can result in the value being unstable or irqs firing repeatedly
122 unless the line is debounced.
124 Debouncing in practice involves setting up a timer when something happens on
125 the line, wait a little while and then sample the line again, so see if it
127 state machine, waiting for a line to become stable. In either case, it sets
133 -----------------------------------------
135 Open drain (CMOS) or open collector (TTL) means the line is not actively driven
137 is not open, it will present a high-impedance (tristate) to the external rail::
142 ||--- out +--- out
143 in ----|| |/
144 ||--+ in ----|
150 - Level-shifting: to reach a logical level higher than that of the silicon
153 - Inverse wire-OR on an I/O line, for example a GPIO line, making it possible
154 for any driving stage on the line to drive it low even if any other output
155 to the same line is simultaneously driving it high. A special case of this
157 wire-OR bus.
159 Both use cases require that the line be equipped with a pull-up resistor. This
160 resistor will make the line tend to high level unless one of the transistors on
163 The level on the line will go as high as the VDD on the pull-up resistor, which
165 level-shift to the higher VDD.
167 Integrated electronics often have an output driver stage in the form of a CMOS
168 "totem-pole" with one N-MOS and one P-MOS transistor where one of them drives
169 the line high and one of them drives the line low. This is called a push-pull
170 output. The "totem-pole" looks like so::
174 OD ||--+
175 +--/ ---o|| P-MOS-FET
176 | ||--+
177 IN --+ +----- out
178 | ||--+
179 +--/ ----|| N-MOS-FET
180 OS ||--+
185 arrives at IN. The switches named "OD" and "OS" are normally closed, creating
186 a push-pull circuit.
189 P-MOS or N-MOS transistor right after the split of the input. As you can see,
190 either transistor will go totally numb if this switch is open. The totem-pole
191 is then halved and give high impedance instead of actively driving the line
192 high or low respectively. That is usually how software-controlled open
195 Some GPIO hardware come in open drain / open source configuration. Some are
196 hard-wired lines that will only support open drain or open source no matter
197 what: there is only one transistor there. Some are software-configurable:
198 by flipping a bit in a register the output can be configured as open drain
199 or open source, in practice by flicking open the switches labeled "OD" and "OS"
200 in the drawing above.
202 By disabling the P-MOS transistor, the output can be driven between GND and
203 high impedance (open drain), and by disabling the N-MOS transistor, the output
204 can be driven between VDD and high impedance (open source). In the first case,
205 a pull-up resistor is needed on the outgoing rail to complete the circuit, and
206 in the second case, a pull-down resistor is needed on the rail.
209 special callback in the gpio_chip: .set_config() that takes a generic
210 pinconf packed value telling whether to configure the line as open drain,
211 open source or push-pull. This will happen in response to the
212 GPIO_OPEN_DRAIN or GPIO_OPEN_SOURCE flag set in the machine file, or coming
215 If this state can not be configured in hardware, i.e. if the GPIO hardware does
216 not support open drain/open source in hardware, the GPIO library will instead
217 use a trick: when a line is set as output, if the line is flagged as open
218 drain, and the IN output value is low, it will be driven low as usual. But
219 if the IN output value is set to high, it will instead *NOT* be driven high,
223 when switching the mode of the line.
226 of actively driving the line low, it is set to input.
230 ---------------------------------------------
232 A GPIO line can support pull-up/down using the .set_config() callback. This
233 means that a pull up or pull-down resistor is available on the output of the
234 GPIO line, and this resistor is software controlled.
236 In discrete designs, a pull-up or pull-down resistor is simply soldered on
237 the circuit board. This is not something we deal with or model in software. The
243 switch a bit in a register enabling or disabling pull-up or pull-down.
245 If the GPIO line supports shunting in different resistance values for the
246 pull-up or pull-down resistor, the GPIO chip callback .set_config() will not
250 different pull-up or pull-down resistance values.
257 most often cascaded off a parent interrupt controller, and in some special
261 the header <linux/irq.h>. So this combined driver is utilizing two sub-
270 certain GPIO line and should not be relied upon to have been called before
273 Always prepare the hardware and make it ready for action in respective
277 We can divide GPIO irqchips in two broad categories:
279 - CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
280 interrupt output line, which is triggered by any enabled GPIO line on that
281 chip. The interrupt output line will then be routed to an parent interrupt
282 controller one level up, in the most simple case the systems primary
284 inside the GPIO controller to figure out which line fired it. The irqchip
292 - HIERARCHICAL INTERRUPT CHIPS: this means that each GPIO line has a dedicated
293 irq line to a parent interrupt controller one level up. There is no need
294 to inquire the GPIO hardware to figure out which line has fired, but it
302 - spinlock_t should be replaced with raw_spinlock_t.[1]
303 - If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
309 ----------------------
311 Cascaded GPIO irqchips usually fall in one of three categories:
313 - CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
315 gets called in a chain from the parent IRQ handler, most typically the
319 sequence in its interrupt handler::
327 struct gpio_chip, as everything happens directly in the callbacks: no
331 threaded on -RT. As a result, spinlock_t or any sleepable APIs (like PM
332 runtime) can't be used in a chained IRQ handler.
336 this way it will become a threaded IRQ handler on -RT and a hard IRQ handler
337 on non-RT (for example, see [3]).
347 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
348 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
349 raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
351 - GENERIC CHAINED GPIO IRQCHIPS: these are the same as "CHAINED GPIO irqchips",
354 The GPIO irqchip will then end up calling something like this sequence in
361 Realtime considerations: this kind of handlers will be forced threaded on -RT,
363 with IRQ enabled and the same work-around as for "CHAINED GPIO irqchips" can
366 - NESTED THREADED GPIO IRQCHIPS: these are off-chip GPIO expanders and any
371 similar, traffic which may in turn incur other IRQs to happen, cannot be
372 handled in a quick IRQ handler with IRQs disabled. Instead they need to spawn
373 a thread and then mask the parent IRQ line until the interrupt is handled
375 this in its interrupt handler::
390 ----------------------------------------
392 To help out in handling the set-up and management of GPIO irqchips and the
397 under the assumption that your interrupts are 1-to-1-mapped to the
398 GPIO line index:
400 .. csv-table::
401 :header: GPIO line offset, Hardware IRQ
407 ngpio-1, ngpio-1
411 and the flag need_valid_mask in gpio_irq_chip can be used to mask off some
414 The preferred way to set up the helpers is to fill in the
422 .. code-block:: c
479 girq = &g->gc.irq;
481 girq->parent_handler = ftgpio_gpio_irq_handler;
482 girq->num_parents = 1;
483 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
485 if (!girq->parents)
486 return -ENOMEM;
487 girq->default_type = IRQ_TYPE_NONE;
488 girq->handler = handle_bad_irq;
489 girq->parents[0] = irq;
491 return devm_gpiochip_add_data(dev, &g->gc, g);
496 .. code-block:: c
553 IRQF_ONESHOT, "my-chip", g);
558 girq = &g->gc.irq;
560 /* This will let us handle the parent IRQ in the driver */
561 girq->parent_handler = NULL;
562 girq->num_parents = 0;
563 girq->parents = NULL;
564 girq->default_type = IRQ_TYPE_NONE;
565 girq->handler = handle_bad_irq;
567 return devm_gpiochip_add_data(dev, &g->gc, g);
570 In this case the typical set-up will look like this:
572 .. code-block:: c
632 girq = &g->gc.irq;
634 girq->default_type = IRQ_TYPE_NONE;
635 girq->handler = handle_bad_irq;
636 girq->fwnode = g->fwnode;
637 girq->parent_domain = parent;
638 girq->child_to_parent_hwirq = my_gpio_child_to_parent_hwirq;
640 return devm_gpiochip_add_data(dev, &g->gc, g);
646 As always it is good to look at examples in the kernel tree for advice
652 .irq.valid_mask with as many bits set as there are GPIO lines in the chip, each
653 bit representing line 0..n-1. Drivers can exclude GPIO lines by clearing bits
654 from this mask. The mask can be filled in the init_valid_mask() callback
657 To use the helpers please keep the following in mind:
659 - Make sure to assign all relevant members of the struct gpio_chip so that
663 - Nominally set gpio_irq_chip.handler to handle_bad_irq. Then, if your irqchip
665 in the irqchip .set_type() callback depending on what your controller
670 -----------------
673 use cases. For example a GPIO line used for IRQs should be an input line,
677 resource (a certain GPIO line and register for example) it needs to deny
685 This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
691 typically be called in the .startup() and .shutdown() callbacks from the
699 ---------------------------
701 In some (fringe) use cases, a driver may be using a GPIO line as input for IRQs,
702 but occasionally switch that line over to drive output and then back to being
707 the IRQ is enabled or disabled. In order to inform gpiolib about this,
718 typically be called in the .irq_disable() and .irq_enable() callbacks from the
726 Real-Time compliance for GPIO IRQ chips
727 ---------------------------------------
729 Any provider of irqchips needs to be carefully tailored to support Real-Time
730 preemption. It is desirable that all irqchips in the GPIO subsystem keep this
731 in mind and do the proper testing to assure they are real time-enabled.
733 So, pay attention on above realtime considerations in the documentation.
735 The following is a checklist to follow when preparing a driver for real-time
738 - ensure spinlock_t is not used as part irq_chip implementation
739 - ensure that sleepable APIs are not used as part irq_chip implementation
742 - Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
744 - Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
745 apply corresponding work-around
746 - Chained GPIO irqchips: get rid of the chained IRQ handler and use generic irq
748 - regmap_mmio: it is possible to disable internal locking in regmap by setting
749 .disable_locking and handling the locking in the GPIO driver
750 - Test your driver with the appropriate in-kernel real-time test cases for both
753 * [1] http://www.spinics.net/lists/linux-omap/msg120425.html
754 * [2] https://lore.kernel.org/r/1443209283-20781-2-git-send-email-[email protected]
755 * [3] https://lore.kernel.org/r/1443209283-20781-3-git-send-email-[email protected]
758 Requesting self-owned GPIO pins