Lines Matching +full:pcie +full:- +full:root +full:- +full:port +full:- +full:1
1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
31 Each PCIe Switch in the path between the root and an endpoint introduces a point
33 given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
43 # cxl list -BEMPu -b cxl_test
49 "port":"port5",
50 "host":"cxl_host_bridge.1",
53 "port":"port8",
54 "host":"cxl_switch_uport.1",
64 "numa_node":1,
65 "host":"cxl_mem.1"
76 "numa_node":1,
83 "port":"port12",
94 "numa_node":1,
106 "numa_node":1,
115 "port":"port4",
119 "port":"port6",
149 "port":"port10",
183 In that listing each "root", "port", and "endpoint" object correspond a kernel
185 its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
191 metadata that determine RAID set assembly. CXL Port topology and CXL Port link
192 status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated
193 by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches
194 the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port
195 objects. Conversely for hot-unplug / removal scenarios, there is no need for
196 the Linux PCI core to tear down switch-level CXL resources because the endpoint
197 ->remove() event cleans up the port data that was established to support that
200 The port metadata and potential decode schemes that a give memory device may
203 # cxl list -BDMu -d root -m mem3
209 "decoder":"decoder3.1",
227 "nr_targets":1
234 "nr_targets":1
261 # cxl list -MDu -d 3.2
300 "root decoders":[
306 "nr_targets":1
320 -----------------
322 .. kernel-doc:: drivers/cxl/pci.c
325 .. kernel-doc:: drivers/cxl/pci.c
328 .. kernel-doc:: drivers/cxl/mem.c
331 .. kernel-doc:: drivers/cxl/cxlmem.h
334 .. kernel-doc:: drivers/cxl/core/memdev.c
337 CXL Port
338 --------
339 .. kernel-doc:: drivers/cxl/port.c
340 :doc: cxl port
343 --------
344 .. kernel-doc:: drivers/cxl/cxl.h
347 .. kernel-doc:: drivers/cxl/cxl.h
350 .. kernel-doc:: drivers/cxl/core/hdm.c
353 .. kernel-doc:: drivers/cxl/core/hdm.c
356 .. kernel-doc:: drivers/cxl/core/cdat.c
359 .. kernel-doc:: drivers/cxl/core/port.c
362 .. kernel-doc:: drivers/cxl/core/port.c
365 .. kernel-doc:: drivers/cxl/core/pci.c
368 .. kernel-doc:: drivers/cxl/core/pci.c
371 .. kernel-doc:: drivers/cxl/core/pmem.c
374 .. kernel-doc:: drivers/cxl/core/regs.c
377 .. kernel-doc:: drivers/cxl/core/mbox.c
381 -----------
382 .. kernel-doc:: drivers/cxl/core/region.c
385 .. kernel-doc:: drivers/cxl/core/region.c
392 -------------------
394 .. kernel-doc:: include/uapi/linux/cxl_mem.h
397 .. kernel-doc:: include/uapi/linux/cxl_mem.h