Lines Matching +full:2 +full:mb
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
61 "pmem_size":"256.00 MiB (268.44 MB)",
62 "ram_size":"256.00 MiB (268.44 MB)",
73 "pmem_size":"256.00 MiB (268.44 MB)",
74 "ram_size":"256.00 MiB (268.44 MB)",
91 "pmem_size":"256.00 MiB (268.44 MB)",
92 "ram_size":"256.00 MiB (268.44 MB)",
103 "pmem_size":"256.00 MiB (268.44 MB)",
104 "ram_size":"256.00 MiB (268.44 MB)",
127 "pmem_size":"256.00 MiB (268.44 MB)",
128 "ram_size":"256.00 MiB (268.44 MB)",
139 "pmem_size":"256.00 MiB (268.44 MB)",
140 "ram_size":"256.00 MiB (268.44 MB)",
150 "host":"cxl_switch_uport.2",
157 "pmem_size":"256.00 MiB (268.44 MB)",
158 "ram_size":"256.00 MiB (268.44 MB)",
169 "pmem_size":"256.00 MiB (268.44 MB)",
170 "ram_size":"256.00 MiB (268.44 MB)",
173 "host":"cxl_mem.2"
211 "size":"512.00 MiB (536.87 MB)",
213 "nr_targets":2
218 "size":"512.00 MiB (536.87 MB)",
220 "nr_targets":2
225 "size":"256.00 MiB (268.44 MB)",
230 "decoder":"decoder3.2",
232 "size":"256.00 MiB (268.44 MB)",
240 "pmem_size":"256.00 MiB (268.44 MB)",
241 "ram_size":"256.00 MiB (268.44 MB)",
244 "host":"cxl_mem.2"
255 memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
267 "pmem_size":"256.00 MiB (268.44 MB)",
268 "ram_size":"256.00 MiB (268.44 MB)",
275 "pmem_size":"256.00 MiB (268.44 MB)",
276 "ram_size":"256.00 MiB (268.44 MB)",
283 "pmem_size":"256.00 MiB (268.44 MB)",
284 "ram_size":"256.00 MiB (268.44 MB)",
291 "pmem_size":"256.00 MiB (268.44 MB)",
292 "ram_size":"256.00 MiB (268.44 MB)",
295 "host":"cxl_mem.2"
302 "decoder":"decoder3.2",
304 "size":"256.00 MiB (268.44 MB)",