Lines Matching +full:gcc +full:- +full:sc8280xp
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <[email protected]>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq5424-dwc3
20 - qcom,ipq6018-dwc3
21 - qcom,ipq8064-dwc3
22 - qcom,ipq8074-dwc3
23 - qcom,ipq9574-dwc3
24 - qcom,msm8953-dwc3
25 - qcom,msm8994-dwc3
26 - qcom,msm8996-dwc3
27 - qcom,msm8998-dwc3
28 - qcom,qcm2290-dwc3
29 - qcom,qcs404-dwc3
30 - qcom,qcs615-dwc3
31 - qcom,qcs8300-dwc3
32 - qcom,qdu1000-dwc3
33 - qcom,sa8775p-dwc3
34 - qcom,sar2130p-dwc3
35 - qcom,sc7180-dwc3
36 - qcom,sc7280-dwc3
37 - qcom,sc8180x-dwc3
38 - qcom,sc8180x-dwc3-mp
39 - qcom,sc8280xp-dwc3
40 - qcom,sc8280xp-dwc3-mp
41 - qcom,sdm660-dwc3
42 - qcom,sdm670-dwc3
43 - qcom,sdm845-dwc3
44 - qcom,sdx55-dwc3
45 - qcom,sdx65-dwc3
46 - qcom,sdx75-dwc3
47 - qcom,sm4250-dwc3
48 - qcom,sm6115-dwc3
49 - qcom,sm6125-dwc3
50 - qcom,sm6350-dwc3
51 - qcom,sm6375-dwc3
52 - qcom,sm8150-dwc3
53 - qcom,sm8250-dwc3
54 - qcom,sm8350-dwc3
55 - qcom,sm8450-dwc3
56 - qcom,sm8550-dwc3
57 - qcom,sm8650-dwc3
58 - qcom,x1e80100-dwc3
59 - qcom,x1e80100-dwc3-mp
60 - const: qcom,dwc3
66 "#address-cells":
69 "#size-cells":
74 power-domains:
78 required-opps:
84 - cfg_noc:: System Config NOC clock.
85 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
87 - iface:: System bus AXI clock.
88 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
90 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
95 clock-names:
105 interconnect-names:
107 - const: usb-ddr
108 - const: apps-usb
113 - pwr_event: Used for wakeup based on other power events.
114 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
118 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
123 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
125 only on SoCs with non-QUSB2 targets with
127 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
131 interrupt-names:
135 qcom,select-utmi-as-pipe-clk:
142 wakeup-source: true
147 "^usb@[0-9a-f]+$":
152 wakeup-source: false
155 - compatible
156 - reg
157 - "#address-cells"
158 - "#size-cells"
159 - ranges
160 - clocks
161 - clock-names
162 - interrupts
163 - interrupt-names
166 - if:
171 - qcom,ipq4019-dwc3
172 - qcom,ipq5332-dwc3
177 clock-names:
179 - const: core
180 - const: sleep
181 - const: mock_utmi
183 - if:
188 - qcom,ipq8064-dwc3
193 - description: Master/Core clock, has to be >= 125 MHz
195 clock-names:
197 - const: core
199 - if:
204 - qcom,ipq9574-dwc3
205 - qcom,msm8953-dwc3
206 - qcom,msm8996-dwc3
207 - qcom,msm8998-dwc3
208 - qcom,qcs8300-dwc3
209 - qcom,sa8775p-dwc3
210 - qcom,sc7180-dwc3
211 - qcom,sc7280-dwc3
212 - qcom,sdm670-dwc3
213 - qcom,sdm845-dwc3
214 - qcom,sdx55-dwc3
215 - qcom,sdx65-dwc3
216 - qcom,sdx75-dwc3
217 - qcom,sm6350-dwc3
222 clock-names:
224 - const: cfg_noc
225 - const: core
226 - const: iface
227 - const: sleep
228 - const: mock_utmi
230 - if:
235 - qcom,ipq6018-dwc3
241 clock-names:
243 - items:
244 - const: core
245 - const: sleep
246 - const: mock_utmi
247 - items:
248 - const: cfg_noc
249 - const: core
250 - const: sleep
251 - const: mock_utmi
253 - if:
258 - qcom,ipq8074-dwc3
259 - qcom,qdu1000-dwc3
264 clock-names:
266 - const: cfg_noc
267 - const: core
268 - const: sleep
269 - const: mock_utmi
271 - if:
276 - qcom,ipq5018-dwc3
277 - qcom,msm8994-dwc3
278 - qcom,qcs404-dwc3
283 clock-names:
285 - const: core
286 - const: iface
287 - const: sleep
288 - const: mock_utmi
290 - if:
295 - qcom,sc8280xp-dwc3
296 - qcom,sc8280xp-dwc3-mp
297 - qcom,x1e80100-dwc3
298 - qcom,x1e80100-dwc3-mp
303 clock-names:
305 - const: cfg_noc
306 - const: core
307 - const: iface
308 - const: sleep
309 - const: mock_utmi
310 - const: noc_aggr
311 - const: noc_aggr_north
312 - const: noc_aggr_south
313 - const: noc_sys
315 - if:
320 - qcom,sdm660-dwc3
326 clock-names:
328 - items:
329 - const: cfg_noc
330 - const: core
331 - const: iface
332 - const: sleep
333 - const: mock_utmi
334 - items:
335 - const: cfg_noc
336 - const: core
337 - const: sleep
338 - const: mock_utmi
340 - if:
345 - qcom,qcm2290-dwc3
346 - qcom,qcs615-dwc3
347 - qcom,sar2130p-dwc3
348 - qcom,sc8180x-dwc3
349 - qcom,sc8180x-dwc3-mp
350 - qcom,sm6115-dwc3
351 - qcom,sm6125-dwc3
352 - qcom,sm8150-dwc3
353 - qcom,sm8250-dwc3
354 - qcom,sm8450-dwc3
355 - qcom,sm8550-dwc3
356 - qcom,sm8650-dwc3
361 clock-names:
363 - const: cfg_noc
364 - const: core
365 - const: iface
366 - const: sleep
367 - const: mock_utmi
368 - const: xo
370 - if:
375 - qcom,sm8350-dwc3
381 clock-names:
384 - const: cfg_noc
385 - const: core
386 - const: iface
387 - const: sleep
388 - const: mock_utmi
389 - const: xo
391 - if:
396 - qcom,ipq5018-dwc3
397 - qcom,ipq6018-dwc3
398 - qcom,ipq8074-dwc3
399 - qcom,msm8953-dwc3
400 - qcom,msm8998-dwc3
406 interrupt-names:
408 - const: pwr_event
409 - const: qusb2_phy
410 - const: ss_phy_irq
412 - if:
417 - qcom,msm8996-dwc3
418 - qcom,qcs404-dwc3
419 - qcom,sdm660-dwc3
420 - qcom,sm6115-dwc3
421 - qcom,sm6125-dwc3
427 interrupt-names:
429 - const: pwr_event
430 - const: qusb2_phy
431 - const: hs_phy_irq
432 - const: ss_phy_irq
434 - if:
439 - qcom,ipq5332-dwc3
444 interrupt-names:
446 - const: pwr_event
447 - const: dp_hs_phy_irq
448 - const: dm_hs_phy_irq
450 - if:
455 - qcom,x1e80100-dwc3
461 interrupt-names:
464 - const: pwr_event
465 - const: dp_hs_phy_irq
466 - const: dm_hs_phy_irq
467 - const: ss_phy_irq
469 - if:
474 - qcom,ipq4019-dwc3
475 - qcom,ipq8064-dwc3
476 - qcom,msm8994-dwc3
477 - qcom,qcs615-dwc3
478 - qcom,qcs8300-dwc3
479 - qcom,qdu1000-dwc3
480 - qcom,sa8775p-dwc3
481 - qcom,sc7180-dwc3
482 - qcom,sc7280-dwc3
483 - qcom,sc8180x-dwc3
484 - qcom,sc8280xp-dwc3
485 - qcom,sdm670-dwc3
486 - qcom,sdm845-dwc3
487 - qcom,sdx55-dwc3
488 - qcom,sdx65-dwc3
489 - qcom,sdx75-dwc3
490 - qcom,sm4250-dwc3
491 - qcom,sm6350-dwc3
492 - qcom,sm8150-dwc3
493 - qcom,sm8250-dwc3
494 - qcom,sm8350-dwc3
495 - qcom,sm8450-dwc3
496 - qcom,sm8550-dwc3
497 - qcom,sm8650-dwc3
503 interrupt-names:
506 - const: pwr_event
507 - const: hs_phy_irq
508 - const: dp_hs_phy_irq
509 - const: dm_hs_phy_irq
510 - const: ss_phy_irq
512 - if:
517 - qcom,sc8180x-dwc3-mp
518 - qcom,x1e80100-dwc3-mp
524 interrupt-names:
526 - const: pwr_event_1
527 - const: pwr_event_2
528 - const: hs_phy_1
529 - const: hs_phy_2
530 - const: dp_hs_phy_1
531 - const: dm_hs_phy_1
532 - const: dp_hs_phy_2
533 - const: dm_hs_phy_2
534 - const: ss_phy_1
535 - const: ss_phy_2
537 - if:
542 - qcom,sc8280xp-dwc3-mp
548 interrupt-names:
550 - const: pwr_event_1
551 - const: pwr_event_2
552 - const: pwr_event_3
553 - const: pwr_event_4
554 - const: hs_phy_1
555 - const: hs_phy_2
556 - const: hs_phy_3
557 - const: hs_phy_4
558 - const: dp_hs_phy_1
559 - const: dm_hs_phy_1
560 - const: dp_hs_phy_2
561 - const: dm_hs_phy_2
562 - const: dp_hs_phy_3
563 - const: dm_hs_phy_3
564 - const: dp_hs_phy_4
565 - const: dm_hs_phy_4
566 - const: ss_phy_1
567 - const: ss_phy_2
572 - |
573 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
574 #include <dt-bindings/interrupt-controller/arm-gic.h>
575 #include <dt-bindings/interrupt-controller/irq.h>
577 #address-cells = <2>;
578 #size-cells = <2>;
581 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
584 #address-cells = <2>;
585 #size-cells = <2>;
587 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
588 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
589 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
590 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
591 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
592 clock-names = "cfg_noc",
598 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
599 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
600 assigned-clock-rates = <19200000>, <150000000>;
607 interrupt-names = "pwr_event", "hs_phy_irq",
610 power-domains = <&gcc USB30_PRIM_GDSC>;
612 resets = <&gcc GCC_USB30_PRIM_BCR>;
622 phy-names = "usb2-phy", "usb3-phy";