Lines Matching +full:41 +full:a

21           # Either a single combined interrupt or up to 14 individual interrupts
25             A list of 14 interrupts; one per each timer channels 0 through 13
43           # Either a single combined interrupt or up to 6 individual interrupts
47             A list of 6 interrupts; one per each of timer channels 1 through 5,
57           # Either a single combined interrupt or up to 4 individual interrupts
61             A list of 4 interrupts; one per timer channel.
69           timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
83           The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
85           trigger a legacy watchdog reset.
88           The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
89           running counter. The first two channels may also trigger a watchdog reset.
120                      <0 41 IRQ_TYPE_LEVEL_HIGH>,
137                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,