Lines Matching +full:big +full:- +full:endian

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shengjiu Wang <[email protected]>
20       - items:
21           - enum:
22               - fsl,imx35-spdif
23               - fsl,imx6sx-spdif
24               - fsl,imx8mm-spdif
25               - fsl,imx8mn-spdif
26               - fsl,imx8mq-spdif
27               - fsl,imx8qm-spdif
28               - fsl,imx8qxp-spdif
29               - fsl,imx8ulp-spdif
30               - fsl,vf610-spdif
31       - items:
32           - enum:
33               - fsl,imx6sl-spdif
34               - fsl,imx6sx-spdif
35           - const: fsl,imx35-spdif
43       - description: Combined or receive interrupt
44       - description: Transmit interrupt
48       - description: DMA controller phandle and request line for RX
49       - description: DMA controller phandle and request line for TX
51   dma-names:
53       - const: rx
54       - const: tx
58       - description: The core clock of spdif controller.
59       - description: Clock for tx0 and rx0.
60       - description: Clock for tx1 and rx1.
61       - description: Clock for tx2 and rx2.
62       - description: Clock for tx3 and rx3.
63       - description: Clock for tx4 and rx4.
64       - description: Clock for tx5 and rx5.
65       - description: Clock for tx6 and rx6.
66       - description: Clock for tx7 and rx7.
67       - description: The spba clock is required when SPDIF is placed as a bus
71       - description: PLL clock source for 8kHz series rate, optional.
72       - description: PLL clock source for 11khz series rate, optional.
75   clock-names:
77       - const: core
78       - const: rxtx0
79       - const: rxtx1
80       - const: rxtx2
81       - const: rxtx3
82       - const: rxtx4
83       - const: rxtx5
84       - const: rxtx6
85       - const: rxtx7
86       - const: spba
87       - const: pll8k
88       - const: pll11k
91   big-endian:
94       If this property is absent, the native endian mode will be in use
95       as default, or the big endian mode will be in use for all the device
96       registers. Set this flag for HCDs with big endian descriptors and big
97       endian registers.
99   power-domains:
103   - compatible
104   - reg
105   - interrupts
106   - dmas
107   - dma-names
108   - clocks
109   - clock-names
114   - if:
118             - fsl,imx8qm-spdif
119             - fsl,imx8qxp-spdif
129   - if:
134               - fsl,imx8qm-spdif
135               - fsl,imx8qxp-spdif
138         - power-domains
141   - |
143         compatible = "fsl,imx35-spdif";
148         dma-names = "rx", "tx";
154         clock-names = "core", "rxtx0",
159         big-endian;