Lines Matching +full:use +full:- +full:dma +full:- +full:rx
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <[email protected]>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
19 - fsl,imx25-uart
20 - fsl,imx27-uart
21 - fsl,imx31-uart
22 - fsl,imx35-uart
23 - fsl,imx50-uart
24 - fsl,imx51-uart
25 - fsl,imx53-uart
26 - fsl,imx6q-uart
27 - const: fsl,imx21-uart
28 - items:
29 - enum:
30 - fsl,imx6sl-uart
31 - fsl,imx6sll-uart
32 - fsl,imx6sx-uart
33 - const: fsl,imx6q-uart
34 - const: fsl,imx21-uart
35 - items:
36 - enum:
37 - fsl,imx6ul-uart
38 - fsl,imx7d-uart
39 - fsl,imx8mm-uart
40 - fsl,imx8mn-uart
41 - fsl,imx8mp-uart
42 - fsl,imx8mq-uart
43 - const: fsl,imx6q-uart
51 clock-names:
53 - const: ipg
54 - const: per
58 - description: DMA controller phandle and request line for RX
59 - description: DMA controller phandle and request line for TX
61 dma-names:
63 - const: rx
64 - const: tx
68 - description: UART RX Interrupt
69 - description: UART TX Interrupt
70 - description: UART RTS Interrupt
73 wakeup-source: true
75 fsl,dte-mode:
80 fsl,inverted-tx:
87 fsl,inverted-rx:
94 fsl,dma-info:
95 $ref: /schemas/types.yaml#/definitions/uint32-array
99 First cell contains the size of DMA buffer chunks, second cell contains
102 When not being configured the system will use default settings, which
103 are sensible for most use cases. If you need low latency processing on
107 - compatible
108 - reg
109 - clocks
110 - clock-names
111 - interrupts
114 - $ref: serial.yaml#
115 - $ref: rs485.yaml#
117 - if:
121 const: fsl,imx1-uart
135 - |
136 #include <dt-bindings/clock/imx5-clock.h>
143 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
148 clock-names = "ipg", "per";
150 dma-names = "rx", "tx";
151 uart-has-rtscts;
152 fsl,dte-mode;