Lines Matching +full:can +full:- +full:primary

4 - compatible : compatible list, may contain one or two entries
5   The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6   etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7   "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
9   provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
21   be set as edge sensitive.  If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26   msi interrupt can be used in the 256 msi interrupts. This property is
27   optional, without this, all the MSI interrupts can be used.
33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
44 		compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
46 		msi-available-ranges = <0 0x100>;
56 		interrupt-parent = <&mpic>;
60 		compatible = "fsl,mpic-msi-v4.3";
81 The Freescale hypervisor and msi-address-64
82 -------------------------------------------
94 In the PAMU, each PCI controller is given only one primary window.  The
95 PAMU restricts DMA operations so that they can only occur within a window.
96 Because PCI devices must be able to DMA to memory, the primary window must
99 PAMU primary windows can be divided into 256 subwindows, and each
100 subwindow can have its own address mapping ("guest physical" to "true
107 primary window used for memory, but mapped to the MSIR block (where MSIIR
109 this.  The address specified in the msi-address-64 property is the PCI