Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <[email protected]>
11 - Lad Prabhakar <prabhakar.mahadev-[email protected]>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
18 (port mode) or in alternate function mode.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
27 - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
28 - renesas,r9a08g045-pinctrl # RZ/G3S
29 - renesas,r9a09g047-pinctrl # RZ/G3E
30 - renesas,r9a09g057-pinctrl # RZ/V2H(P)
32 - items:
33 - enum:
34 - renesas,r9a07g054-pinctrl # RZ/V2L
35 - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
40 gpio-controller: true
42 '#gpio-cells':
45 The first cell contains the global GPIO port index, constructed using the
46 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
50 gpio-ranges:
53 interrupt-controller: true
55 '#interrupt-cells':
58 The first cell contains the global GPIO port index, constructed using the
59 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
67 power-domains:
72 - items:
73 - description: GPIO_RSTN signal
74 - description: GPIO_PORT_RESETN signal
75 - description: GPIO_SPARE_RESETN signal
76 - items:
77 - description: PFC main reset
78 - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
82 - type: object
85 - $ref: pincfg-node.yaml#
86 - $ref: pinmux-node.yaml#
96 Values are constructed from GPIO port number, pin number, and
98 helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
100 drive-strength:
102 drive-strength-microamp:
106 output-impedance-ohms:
108 power-source:
111 slew-rate: true
112 gpio-hog: true
115 input-enable: true
116 output-enable: true
117 output-high: true
118 output-low: true
119 line-name: true
120 bias-disable: true
121 bias-pull-down: true
122 bias-pull-up: true
123 input-schmitt-enable: true
124 input-schmitt-disable: true
125 drive-open-drain: true
126 drive-push-pull: true
127 renesas,output-impedance:
131 register, which adjusts the drive strength value and is pin-dependent.
135 - type: object
140 - $ref: pinctrl.yaml#
142 - if:
147 - renesas,r9a09g047-pinctrl
148 - renesas,r9a09g057-pinctrl
159 - compatible
160 - reg
161 - gpio-controller
162 - '#gpio-cells'
163 - gpio-ranges
164 - interrupt-controller
165 - '#interrupt-cells'
166 - clocks
167 - power-domains
168 - resets
171 - |
172 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
173 #include <dt-bindings/clock/r9a07g044-cpg.h>
176 compatible = "renesas,r9a07g044-pinctrl";
179 gpio-controller;
180 #gpio-cells = <2>;
181 gpio-ranges = <&pinctrl 0 0 392>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
188 power-domains = <&cpg>;
197 input-enable;
200 sd1-pwr-en-hog {
201 gpio-hog;
203 output-high;
204 line-name = "sd1_pwr_en";
211 power-source = <3300>;
216 power-source = <3300>;
221 power-source = <3300>;