Lines Matching +full:qcom +full:- +full:sdm845 +full:- +full:tlmm +full:- +full:state
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 TLMM pin controller
10 - Bjorn Andersson <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
14 Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,sdm845-pinctrl
29 gpio-reserved-ranges:
33 gpio-line-names:
37 "-state$":
39 - $ref: "#/$defs/qcom-sdm845-tlmm-state"
40 - patternProperties:
41 "-pins$":
42 $ref: "#/$defs/qcom-sdm845-tlmm-state"
45 "-hog(-[0-9]+)?$":
48 - gpio-hog
51 qcom-sdm845-tlmm-state:
56 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
67 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
100 - pins
103 - compatible
104 - reg
109 - |
110 #include <dt-bindings/gpio/gpio.h>
111 #include <dt-bindings/interrupt-controller/arm-gic.h>
114 compatible = "qcom,sdm845-pinctrl";
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 gpio-ranges = <&tlmm 0 0 151>;
122 wakeup-parent = <&pdc_intc>;
124 ap-suspend-l-hog {
125 gpio-hog;
127 output-low;
130 cci0-default-state {
134 bias-pull-up;
135 drive-strength = <2>;
138 cam0-default-state {
139 rst-pins {
143 drive-strength = <16>;
144 bias-disable;
147 mclk0-pins {
151 drive-strength = <16>;
152 bias-disable;