Lines Matching +full:qcom +full:- +full:sdm630 +full:- +full:tlmm +full:- +full:state
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM630 and SDM660 TLMM pin controller
10 - Bjorn Andersson <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
14 Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 - qcom,sdm630-pinctrl
23 - qcom,sdm660-pinctrl
28 reg-names:
30 - const: south
31 - const: center
32 - const: north
37 gpio-reserved-ranges:
41 gpio-line-names:
45 "-state$":
47 - $ref: "#/$defs/qcom-sdm630-tlmm-state"
48 - patternProperties:
49 "-pins$":
50 $ref: "#/$defs/qcom-sdm630-tlmm-state"
54 qcom-sdm630-tlmm-state:
59 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
69 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
70 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
119 - pins
122 - compatible
123 - reg
128 - |
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
131 tlmm: pinctrl@3100000 {
132 compatible = "qcom,sdm630-pinctrl";
136 reg-names = "south", "center", "north";
138 gpio-controller;
139 gpio-ranges = <&tlmm 0 0 114>;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <2>;
144 blsp1-uart1-default-state {
147 drive-strength = <2>;
148 bias-disable;
151 blsp2_uart1_default: blsp2-uart1-active-state {
152 tx-rts-pins {
155 drive-strength = <2>;
156 bias-disable;
159 rx-pins {
162 drive-strength = <2>;
163 bias-pull-up;
166 cts-pins {
169 drive-strength = <2>;
170 bias-pull-down;