Lines Matching +full:phy +full:- +full:output +full:- +full:reference +full:- +full:clock

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Christian Bruel <[email protected]>
13   Single lane PHY shared (exclusive) between the USB3 and PCIe controllers.
18     const: st,stm32mp25-combophy
23   "#phy-cells":
29       - description: apb Bus clock mandatory to access registers.
30       - description: ker Internal RCC reference clock for USB3 or PCIe
31       - description: pad Optional on board clock input for PCIe only. Typically an
32                      external 100Mhz oscillator wired on dedicated CLKIN pad. Used as reference
33                      clock input instead of the ker
35   clock-names:
38       - const: apb
39       - const: ker
40       - const: pad
45   reset-names:
46     const: phy
48   power-domains:
51   wakeup-source: true
57   access-controllers:
61   st,ssc-on:
66   st,rx-equalizer:
74   st,output-micro-ohms:
79       A value property to tune the Single Ended Output Impedance, simulations results
82   st,output-vswing-microvolt:
87       A value property in microvolt to tune the Single Ended Output Voltage Swing to change the
91   - compatible
92   - reg
93   - "#phy-cells"
94   - clocks
95   - clock-names
96   - resets
97   - reset-names
102   - |
103     #include <dt-bindings/clock/st,stm32mp25-rcc.h>
104     #include <dt-bindings/interrupt-controller/arm-gic.h>
105     #include <dt-bindings/reset/st,stm32mp25-rcc.h>
107     phy@480c0000 {
108         compatible = "st,stm32mp25-combophy";
110         #phy-cells = <1>;
112         clock-names = "apb", "ker";
114         reset-names = "phy";
115         access-controllers = <&rifsc 67>;
116         power-domains = <&CLUSTER_PD>;
117         wakeup-source;
118         interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;