Lines Matching +full:rx +full:- +full:equalizer
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Daniel Machon <[email protected]>
19 * RX Adaptive Decision Feedback Equalizer (DFE)
20 * Programmable continuous time linear equalizer (CTLE)
21 * Rx variable gain control
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
23 * Adjustable tx de-emphasis (FFE)
25 * Supports rx eye monitor
32 The SERDES6G is a high-speed SERDES interface, which can operate at
35 * 100 Mbps (100BASE-FX)
36 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
37 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
38 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
42 The SERDES10G is a high-speed SERDES interface, which can operate at
45 * 100 Mbps (100BASE-FX)
46 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
47 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
49 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
50 * 10 Gbps (10G-USGMII)
51 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
55 The SERDES25G is a high-speed SERDES interface, which can operate at
58 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
59 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
61 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
62 * 10 Gbps (10G-USGMII)
63 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
64 * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
71 pattern: "^serdes@[0-9a-f]+$"
75 - enum:
76 - microchip,sparx5-serdes
77 - microchip,lan9691-serdes
78 - items:
79 - enum:
80 - microchip,lan9698-serdes
81 - microchip,lan9696-serdes
82 - microchip,lan9694-serdes
83 - microchip,lan9693-serdes
84 - microchip,lan9692-serdes
85 - const: microchip,lan9691-serdes
90 '#phy-cells':
93 - The main serdes input port
99 - compatible
100 - reg
101 - '#phy-cells'
102 - clocks
107 - |
109 compatible = "microchip,sparx5-serdes";
110 #phy-cells = <1>;