Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <[email protected]>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
78 - items:
79 - enum:
80 - mediatek,mt2712-tphy
81 - mediatek,mt7629-tphy
82 - mediatek,mt7986-tphy
83 - mediatek,mt8183-tphy
84 - mediatek,mt8186-tphy
85 - mediatek,mt8192-tphy
86 - mediatek,mt8365-tphy
87 - const: mediatek,generic-tphy-v2
88 - items:
89 - enum:
90 - mediatek,mt8188-tphy
91 - mediatek,mt8195-tphy
92 - const: mediatek,generic-tphy-v3
93 - const: mediatek,mt2701-u3phy
95 - const: mediatek,mt2712-u3phy
97 - const: mediatek,mt8173-u3phy
102 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
103 T-PHY V2/V3, such as mt2712.
106 "#address-cells":
109 "#size-cells":
112 # Used with non-empty value if optional 'reg' is not provided.
114 # (child-bus-address, parent-bus-address, length).
117 mediatek,src-ref-clk-mhz:
122 mediatek,src-coef:
125 $ref: /schemas/types.yaml#/definitions/uint32
128 power-domains:
140 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
143 A sub-node is required for each port the controller provides.
154 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
155 - description: Reference clock of analog phy
158 separated, otherwise uses "ref" clock only if needed.
160 clock-names:
163 - const: ref
164 - const: da_ref
166 "#phy-cells":
171 - description: The PHY type
173 - PHY_TYPE_USB2
174 - PHY_TYPE_USB3
175 - PHY_TYPE_PCIE
176 - PHY_TYPE_SATA
177 - PHY_TYPE_SGMII
179 nvmem-cells:
181 - description: internal R efuse for U2 PHY or U3/PCIe PHY
182 - description: rx_imp_sel efuse for U3/PCIe PHY
183 - description: tx_imp_sel efuse for U3/PCIe PHY
186 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
187 three items should be provided at the same time for U3/PCIe PHY,
189 If unspecified, will use hardware auto-load efuse.
191 nvmem-cell-names:
193 - const: intr
194 - const: rx_imp
195 - const: tx_imp
198 mediatek,eye-src:
200 The value of slew rate calibrate (U2 phy)
201 $ref: /schemas/types.yaml#/definitions/uint32
205 mediatek,eye-vrt:
207 The selection of VRT reference voltage (U2 phy)
208 $ref: /schemas/types.yaml#/definitions/uint32
212 mediatek,eye-term:
214 The selection of HS_TX TERM reference voltage (U2 phy)
215 $ref: /schemas/types.yaml#/definitions/uint32
221 The selection of internal resistor (U2 phy)
222 $ref: /schemas/types.yaml#/definitions/uint32
228 The selection of disconnect threshold (U2 phy)
229 $ref: /schemas/types.yaml#/definitions/uint32
233 mediatek,pre-emphasis:
235 The level of pre-emphasis which used to widen the eye opening and
238 8.3% etc. (U2 phy)
239 $ref: /schemas/types.yaml#/definitions/uint32
248 mediatek,force-mode:
250 The force mode is used to manually switch the shared phy mode between
251 USB3 and PCIe, when USB3 phy type is selected by the consumer, and
252 force-mode is set, will cause phy's power and pipe toggled and force
253 phy as USB3 mode which switched from default PCIe mode. But prefer to
254 use the property "mediatek,syscon-type" for newer SoCs that support it.
257 mediatek,syscon-type:
258 $ref: /schemas/types.yaml#/definitions/phandle-array
265 - description:
267 - description:
269 - description:
274 - reg
275 - "#phy-cells"
280 - compatible
281 - "#address-cells"
282 - "#size-cells"
283 - ranges
288 - |
289 #include <dt-bindings/clock/mt8173-clk.h>
290 #include <dt-bindings/interrupt-controller/arm-gic.h>
291 #include <dt-bindings/interrupt-controller/irq.h>
292 #include <dt-bindings/phy/phy.h>
294 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
296 reg-names = "mac", "ippc";
302 clock-names = "sys_ck";
305 t-phy@11290000 {
306 compatible = "mediatek,mt8173-u3phy";
308 #address-cells = <1>;
309 #size-cells = <1>;
312 u2port0: usb-phy@11290800 {
315 clock-names = "ref", "da_ref";
316 #phy-cells = <1>;
319 u3port0: usb-phy@11290900 {
322 clock-names = "ref";
323 #phy-cells = <1>;
326 u2port1: usb-phy@11291000 {
328 #phy-cells = <1>;