Lines Matching +full:pcie +full:- +full:root +full:- +full:port +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
27 iATU/eDMA registers. The particular sub-space is selected by the
32 is selected. Note the PCIe CFG-space, PL and Shadow registers are
33 specific for each activated function, while the rest of the sub-spaces
38 reg-names:
44 There are two main sub-blocks which are normally capable of
47 Endpoint controllers IRQ-signals, the later interface is obviously
48 Root Complex specific since it's responsible for the incoming MSI
50 responsible for reporting the generic PCIe hierarchy and Root
51 Complex events like VPD IO request, general AER, PME, Hot-plug, link
54 minItems: 1
57 interrupt-names:
58 minItems: 1
63 DWC PCIe reference manual explicitly defines a set of the clocks required
68 minItems: 1
71 clock-names:
72 minItems: 1
76 - description:
77 Data Bus Interface (DBI) clock. Clock signal for the AXI-bus
78 interface of the Configuration-Dependent Module, which is
81 - description:
82 Application AXI-bus Master interface clock. Basically this is
83 a clock for the controller DMA interface (PCI-to-CPU).
85 - description:
86 Application AXI-bus Slave interface clock. This is a clock for
87 the CPU-to-PCI memory IO interface.
89 - description:
90 Controller Core-PCS PIPE interface clock. It's normally
91 supplied by an external PCS-PHY.
93 - description:
97 - description:
102 - description:
108 - description:
110 a PHY-viewport-based interface, but some platform may have
113 - description:
114 Vendor-specific clock names. Consider using the generic names
117 - description: See native 'dbi' clock for details
118 enum: [ pcie, pcie_apb_sys, aclk_dbi ]
119 - description: See native 'mstr/slv' clock for details
121 - description: See native 'pipe' clock for details
123 - description: See native 'aux' clock for details
125 - description: See native 'ref' clock for details.
127 - description: See nativs 'phy_reg' clock for details
132 DWC PCIe reference manual explicitly defines a set of the reset
133 signals required to be de-asserted to properly activate the controller
134 sub-parts. All of these signals can be divided into two sub-groups':'
135 application and core resets with respect to the main sub-domains they
139 minItems: 1
142 reset-names:
143 minItems: 1
147 - description: Data Bus Interface (DBI) domain reset
149 - description: AXI-bus Master interface reset
151 - description: AXI-bus Slave interface reset
153 - description: Application-dependent interface reset
155 - description: Controller Non-sticky CSR flags reset
156 const: non-sticky
157 - description: Controller sticky CSR flags reset
159 - description: PIPE-interface (Core-PCS) logic reset
161 - description:
164 - description: PCS/PHY block reset
166 - description: PMC hot reset signal
168 - description: Cold reset signal
170 - description:
171 Vendor-specific reset names. Consider using the generic names
174 - description: See native 'app' reset for details
176 - description: See native 'phy' reset for details
178 - description: See native 'pwr' reset for details
184 the phandle array in the line-based order. Obviously each the specified
185 PHYs are supposed to be able to work in the PCIe mode with a speed
186 implied by the DWC PCIe controller they are attached to.
187 minItems: 1
190 phy-names:
191 minItems: 1
194 - description: Generic PHY names
196 pattern: '^pcie[0-9]+$'
197 - description:
198 Vendor-specific PHY names. Consider using the generic
202 - pattern: '^pcie(-?phy[0-9]*)?$'
203 - pattern: '^p2u-[0-7]$'
205 reset-gpio:
208 Reference to the GPIO-controlled PERST# signal. It is used to reset all
209 the peripheral devices available on the PCIe bus.
210 maxItems: 1
212 reset-gpios:
214 Reference to the GPIO-controlled PERST# signal. It is used to reset all
215 the peripheral devices available on the PCIe bus.
216 maxItems: 1
218 max-link-speed:
221 num-lanes:
223 Number of PCIe link lanes to use. Can be omitted if the already brought
227 num-ob-windows:
232 auto-detected based on the iATU memory writability. So there is no
233 point in having a dedicated DT-property for it.
236 num-ib-windows:
241 for the outbound AT windows, this parameter can be auto-detected based
243 DT-property for it either.
246 num-viewport:
254 snps,enable-cdm-check:
258 registers for data corruption. CDM registers include standard PCIe
259 configuration space registers, Port Logic registers, DMA and iATU
260 registers. This feature has been available since DWC PCIe v4.80a.
262 dma-coherent: true