Lines Matching +full:x1e80100 +full:- +full:gcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm X1E80100 PCI Express Root Complex
10 - Bjorn Andersson <[email protected]>
11 - Manivannan Sadhasivam <[email protected]>
14 Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
19 const: qcom,pcie-x1e80100
25 reg-names:
27 - const: parf # Qualcomm specific registers
28 - const: dbi # DesignWare PCIe registers
29 - const: elbi # External local bus interface registers
30 - const: atu # ATU address space
31 - const: config # PCIe configuration space
32 - const: mhi # MHI registers
38 clock-names:
40 - const: aux # Auxiliary clock
41 - const: cfg # Configuration clock
42 - const: bus_master # Master AXI clock
43 - const: bus_slave # Slave AXI clock
44 - const: slave_q2a # Slave Q2A clock
45 - const: noc_aggr # Aggre NoC PCIe AXI clock
46 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
52 interrupt-names:
55 - const: msi0
56 - const: msi1
57 - const: msi2
58 - const: msi3
59 - const: msi4
60 - const: msi5
61 - const: msi6
62 - const: msi7
63 - const: global
69 reset-names:
72 - const: pci # PCIe core reset
73 - const: link_down # PCIe link down reset
76 - $ref: qcom,pcie-common.yaml#
81 - |
82 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
83 #include <dt-bindings/gpio/gpio.h>
84 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 #address-cells = <2>;
89 #size-cells = <2>;
92 compatible = "qcom,pcie-x1e80100";
99 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
103 bus-range = <0x00 0xff>;
105 linux,pci-domain = <0>;
106 num-lanes = <2>;
108 #address-cells = <3>;
109 #size-cells = <2>;
111 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
112 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
113 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
114 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
115 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
116 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
117 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
118 clock-names = "aux",
126 dma-coherent;
137 interrupt-names = "msi0", "msi1", "msi2", "msi3",
139 #interrupt-cells = <1>;
140 interrupt-map-mask = <0 0 0 0x7>;
141 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
148 interconnect-names = "pcie-mem", "cpu-pcie";
150 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
154 phy-names = "pciephy";
156 pinctrl-0 = <&pcie0_default_state>;
157 pinctrl-names = "default";
159 power-domains = <&gcc GCC_PCIE_4_GDSC>;
161 resets = <&gcc GCC_PCIE_4_BCR>;
162 reset-names = "pci";
164 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
165 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;