Lines Matching +full:pcie +full:- +full:5
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Manivannan Sadhasivam <[email protected]>
14 Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
20 - const: qcom,pcie-sm8550
21 - items:
22 - enum:
23 - qcom,sar2130p-pcie
24 - qcom,pcie-sm8650
25 - const: qcom,pcie-sm8550
28 minItems: 5
31 reg-names:
32 minItems: 5
34 - const: parf # Qualcomm specific registers
35 - const: dbi # DesignWare PCIe registers
36 - const: elbi # External local bus interface registers
37 - const: atu # ATU address space
38 - const: config # PCIe configuration space
39 - const: mhi # MHI registers
45 clock-names:
48 - const: aux # Auxiliary clock
49 - const: cfg # Configuration clock
50 - const: bus_master # Master AXI clock
51 - const: bus_slave # Slave AXI clock
52 - const: slave_q2a # Slave Q2A clock
53 - const: ddrss_sf_tbu # PCIe SF TBU clock
54 - const: noc_aggr # Aggre NoC PCIe AXI clock
55 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
56 - const: qmip_pcie_ahb # QMIP PCIe AHB clock
62 interrupt-names:
65 - const: msi0
66 - const: msi1
67 - const: msi2
68 - const: msi3
69 - const: msi4
70 - const: msi5
71 - const: msi6
72 - const: msi7
73 - const: global
79 reset-names:
82 - const: pci # PCIe core reset
83 - const: link_down # PCIe link down reset
86 - $ref: qcom,pcie-common.yaml#
91 - |
92 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
93 #include <dt-bindings/gpio/gpio.h>
94 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
98 #address-cells = <2>;
99 #size-cells = <2>;
101 pcie@1c00000 {
102 compatible = "qcom,pcie-sm8550";
108 reg-names = "parf", "dbi", "elbi", "atu", "config";
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
115 num-lanes = <2>;
117 #address-cells = <3>;
118 #size-cells = <2>;
127 clock-names = "aux",
135 dma-coherent;
146 interrupt-names = "msi0", "msi1", "msi2", "msi3",
148 #interrupt-cells = <1>;
149 interrupt-map-mask = <0 0 0 0x7>;
150 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
157 interconnect-names = "pcie-mem", "cpu-pcie";
159 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
163 phy-names = "pciephy";
165 pinctrl-0 = <&pcie0_default_state>;
166 pinctrl-names = "default";
168 power-domains = <&gcc PCIE_0_GDSC>;
171 reset-names = "pci";
173 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
174 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;