Lines Matching +full:gcc +full:- +full:sm8450
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 PCI Express Root Complex
10 - Bjorn Andersson <[email protected]>
11 - Manivannan Sadhasivam <[email protected]>
14 Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
20 - qcom,pcie-sm8450-pcie0
21 - qcom,pcie-sm8450-pcie1
27 reg-names:
30 - const: parf # Qualcomm specific registers
31 - const: dbi # DesignWare PCIe registers
32 - const: elbi # External local bus interface registers
33 - const: atu # ATU address space
34 - const: config # PCIe configuration space
35 - const: mhi # MHI registers
41 clock-names:
44 - const: pipe # PIPE clock
45 - const: pipe_mux # PIPE MUX
46 - const: phy_pipe # PIPE output clock
47 - const: ref # REFERENCE clock
48 - const: aux # Auxiliary clock
49 - const: cfg # Configuration clock
50 - const: bus_master # Master AXI clock
51 - const: bus_slave # Slave AXI clock
52 - const: slave_q2a # Slave Q2A clock
53 - const: ddrss_sf_tbu # PCIe SF TBU clock
54 - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock
55 - const: aggre1 # Aggre NoC PCIe1 AXI clock
61 interrupt-names:
63 - const: msi0
64 - const: msi1
65 - const: msi2
66 - const: msi3
67 - const: msi4
68 - const: msi5
69 - const: msi6
70 - const: msi7
71 - const: global
76 reset-names:
78 - const: pci
81 - $ref: qcom,pcie-common.yaml#
86 - |
87 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
88 #include <dt-bindings/clock/qcom,rpmh.h>
89 #include <dt-bindings/gpio/gpio.h>
90 #include <dt-bindings/interconnect/qcom,sm8450.h>
91 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #address-cells = <2>;
95 #size-cells = <2>;
98 compatible = "qcom,pcie-sm8450-pcie0";
104 reg-names = "parf", "dbi", "elbi", "atu", "config";
108 bus-range = <0x00 0xff>;
110 linux,pci-domain = <0>;
111 max-link-speed = <2>;
112 num-lanes = <1>;
114 #address-cells = <3>;
115 #size-cells = <2>;
117 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
118 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
121 <&gcc GCC_PCIE_0_AUX_CLK>,
122 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
123 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
124 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
125 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
126 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
127 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
128 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
129 clock-names = "pipe",
151 interrupt-names = "msi0", "msi1", "msi2", "msi3",
153 #interrupt-cells = <1>;
154 interrupt-map-mask = <0 0 0 0x7>;
155 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
159 msi-map = <0x0 &gic_its 0x5981 0x1>,
161 msi-map-mask = <0xff00>;
163 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
167 phy-names = "pciephy";
169 pinctrl-0 = <&pcie0_default_state>;
170 pinctrl-names = "default";
172 power-domains = <&gcc PCIE_0_GDSC>;
174 resets = <&gcc GCC_PCIE_0_BCR>;
175 reset-names = "pci";
177 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
178 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;