Lines Matching +full:pcie +full:- +full:root +full:- +full:port +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple PCIe host controller
10 - Mark Kettenis <[email protected]>
13 The Apple PCIe host controller is a PCIe host controller with
14 multiple root ports present in Apple ARM SoC platforms, including
16 The controller incorporates Synopsys DesigWare PCIe logic to
17 implements its root ports. But the ATU found on most DesignWare
18 PCIe host bridges is absent.
20 All root ports share a single ECAM space, but separate GPIOs are
22 the standard "reset-gpios" and "max-link-speed" properties appear on
24 the individual root ports.
26 MSIs are handled by the PCIe controller and translated into regular
28 distributed over the root ports as the OS sees fit by programming
29 the PCIe controller's port registers.
34 - enum:
35 - apple,t8103-pcie
36 - apple,t8112-pcie
37 - apple,t6000-pcie
38 - const: apple,pcie
44 reg-names:
47 - const: config
48 - const: rc
49 - const: port0
50 - const: port1
51 - const: port2
52 - const: port3
60 Interrupt specifiers, one for each root port.
61 minItems: 1
64 msi-parent: true
66 msi-ranges:
67 maxItems: 1
69 iommu-map: true
70 iommu-map-mask: true
72 power-domains:
73 maxItems: 1
76 - compatible
77 - reg
78 - reg-names
79 - bus-range
80 - interrupts
81 - msi-controller
82 - msi-parent
83 - msi-ranges
88 - $ref: /schemas/pci/pci-host-bridge.yaml#
89 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
90 - if:
94 const: apple,t8103-pcie
103 - |
104 #include <dt-bindings/interrupt-controller/apple-aic.h>
107 #address-cells = <2>;
108 #size-cells = <2>;
110 pcie0: pcie@690000000 {
111 compatible = "apple,t8103-pcie", "apple,pcie";
119 reg-names = "config", "rc", "port0", "port1", "port2";
121 interrupt-parent = <&aic>;
126 msi-controller;
127 msi-parent = <&pcie0>;
128 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
130 iommu-map = <0x100 &dart0 1 1>,
131 <0x200 &dart1 1 1>,
132 <0x300 &dart2 1 1>;
133 iommu-map-mask = <0xff00>;
135 bus-range = <0 3>;
136 #address-cells = <3>;
137 #size-cells = <2>;
141 power-domains = <&ps_apcie_gp>;
142 pinctrl-0 = <&pcie_pins>;
143 pinctrl-names = "default";
148 reset-gpios = <&pinctrl_ap 152 0>;
150 #address-cells = <3>;
151 #size-cells = <2>;
155 pci@1,0 {
158 reset-gpios = <&pinctrl_ap 153 0>;
160 #address-cells = <3>;
161 #size-cells = <2>;
168 reset-gpios = <&pinctrl_ap 33 0>;
170 #address-cells = <3>;
171 #size-cells = <2>;