Lines Matching +full:tcam +full:- +full:based
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Lars Povlsen <[email protected]>
12 - Daniel Machon <[email protected]>
15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
16 Enterprise switching features such as advanced TCAM-based VLAN and
18 security through TCAM-based frame processing using versatile content
26 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
29 The SparX-5 switch family targets managed Layer 2 and Layer 3
35 pattern: "^switch@[0-9a-f]+$"
39 - enum:
40 - microchip,lan9691-switch
41 - microchip,sparx5-switch
42 - items:
43 - enum:
44 - microchip,lan969c-switch
45 - microchip,lan969b-switch
46 - microchip,lan969a-switch
47 - microchip,lan9699-switch
48 - microchip,lan9698-switch
49 - microchip,lan9697-switch
50 - microchip,lan9696-switch
51 - microchip,lan9695-switch
52 - microchip,lan9694-switch
53 - microchip,lan9693-switch
54 - microchip,lan9692-switch
55 - const: microchip,lan9691-switch
59 - description: cpu target
60 - description: devices target
61 - description: general control block target
63 reg-names:
65 - const: cpu
66 - const: devices
67 - const: gcb
72 - description: register based extraction
73 - description: frame dma based extraction
74 - description: ptp interrupt
76 interrupt-names:
79 - const: xtr
80 - const: fdma
81 - const: ptp
85 - description: Reset controller used for switch core reset (soft reset)
87 reset-names:
89 - const: switch
91 mac-address: true
93 ethernet-ports:
98 '#address-cells':
100 '#size-cells':
104 "^port@[0-9a-f]+$":
105 $ref: /schemas/net/ethernet-controller.yaml#
123 microchip,sd-sgpio:
132 rx-internal-delay-ps:
141 tx-internal-delay-ps:
151 - reg
152 - phys
153 - phy-mode
154 - microchip,bandwidth
157 - required:
158 - phy-handle
159 - required:
160 - sfp
161 - managed
164 - compatible
165 - reg
166 - reg-names
167 - interrupts
168 - interrupt-names
169 - ethernet-ports
174 - |
175 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 compatible = "microchip,sparx5-switch";
181 reg-names = "cpu", "devices", "gcb";
183 interrupt-names = "xtr";
185 reset-names = "switch";
186 ethernet-ports {
187 #address-cells = <1>;
188 #size-cells = <0>;
194 phy-handle = <&phy0>;
195 phy-mode = "qsgmii";
203 phy-mode = "10gbase-r";
205 managed = "in-band-status";
206 microchip,sd-sgpio = <365>;
212 phy-mode = "10gbase-r";
214 managed = "in-band-status";
215 microchip,sd-sgpio = <369>;
221 phy-mode = "10gbase-r";
223 managed = "in-band-status";
224 microchip,sd-sgpio = <373>;
230 phy-mode = "10gbase-r";
232 managed = "in-band-status";
233 microchip,sd-sgpio = <377>;
240 phy-handle = <&phy64>;
241 phy-mode = "sgmii";
242 mac-address = [ 00 00 00 01 02 03 ];