Lines Matching +full:rmii +full:- +full:clk +full:- +full:internal
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <[email protected]>
11 - Woojung Huh <[email protected]>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
25 - microchip,ksz8864 # 4-port version of KSZ8895 family switch
26 - microchip,ksz8873
27 - microchip,ksz8895 # 5-port version of KSZ8895 family switch
28 - microchip,ksz9477
29 - microchip,ksz9897
30 - microchip,ksz9896
31 - microchip,ksz9567
32 - microchip,ksz8565
33 - microchip,ksz9893
34 - microchip,ksz9563
35 - microchip,ksz8563
36 - microchip,ksz8567
37 - microchip,lan9646
39 reset-gpios:
44 wakeup-source: true
46 microchip,synclko-125:
51 microchip,synclko-disable:
55 microchip,synclko-125.
57 microchip,pme-active-high:
60 Indicates if the PME pin polarity is active-high.
62 microchip,io-drive-strength-microamp:
68 microchip,hi-drive-strength-microamp:
71 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
75 microchip,lo-drive-strength-microamp:
89 mdio-parent-bus:
94 the internal MDIO bus is accessed via a secondary MDIO
98 "^ethernet-phy@[0-9a-f]$":
100 $ref: /schemas/net/ethernet-phy.yaml#
106 - compatible
107 - reg
114 - microchip,ksz8863
115 - microchip,ksz8873
117 $ref: dsa.yaml#/$defs/ethernet-ports
120 "^(ethernet-)?ports$":
122 "^(ethernet-)?port@[0-2]$":
123 $ref: dsa-port.yaml#
126 microchip,rmii-clk-internal:
130 can select between internal and external RMII reference
131 clock. Internal reference clock means that the clock for
132 the RMII of ksz88x3 is provided by the ksz88x3 internally
136 If microchip,rmii-clk-internal is set, ksz88x3 will provide
137 rmii reference clock internally, otherwise reference clock
140 microchip,rmii-clk-internal: [ethernet]
145 - |
146 #include <dt-bindings/gpio/gpio.h>
150 fixed-link {
152 full-duplex;
157 #address-cells = <1>;
158 #size-cells = <0>;
160 pinctrl-0 = <&pinctrl_spi_ksz>;
161 cs-gpios = <&pioC 25 0>;
166 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
168 spi-max-frequency = <44000000>;
170 ethernet-ports {
171 #address-cells = <1>;
172 #size-cells = <0>;
196 phy-mode = "rgmii";
198 fixed-link {
200 full-duplex;
210 spi-max-frequency = <44000000>;
212 ethernet-ports {
213 #address-cells = <1>;
214 #size-cells = <0>;
234 phy-mode = "rgmii";
236 fixed-link {
238 full-duplex;