Lines Matching +full:davinci +full:- +full:nand +full:- +full:buswidth
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DaVinci NAND controller
10 - Marcus Folkesson <[email protected]>
13 - $ref: nand-controller.yaml
18 - ti,davinci-nand
19 - ti,keystone-nand
23 - description: Access window.
24 - description: AEMIF control registers.
29 ti,davinci-chipselect:
32 chipselect is used for accessing the nand.
36 ti,davinci-mask-ale:
39 added to the base address for the chip select space the NAND Flash
44 ti,davinci-mask-cle:
47 added to the base address for the chip select space the NAND Flash device
52 ti,davinci-mask-chipsel:
59 ti,davinci-ecc-bits:
63 ti,davinci-ecc-mode:
64 description: Operation mode of the NAND ECC mode.
66 enum: [none, soft, hw, on-die]
69 ti,davinci-nand-buswidth:
70 description: Bus width to the NAND chip.
76 ti,davinci-nand-use-bbt:
84 - compatible
85 - reg
86 - ti,davinci-chipselect
91 - |
93 #address-cells = <2>;
94 #size-cells = <1>;
96 nand-controller@2000000,0 {
97 compatible = "ti,davinci-nand";
98 #address-cells = <1>;
99 #size-cells = <0>;
103 ti,davinci-chipselect = <1>;
104 ti,davinci-mask-ale = <0>;
105 ti,davinci-mask-cle = <0>;
106 ti,davinci-mask-chipsel = <0>;
108 ti,davinci-nand-buswidth = <16>;
109 ti,davinci-ecc-mode = "hw";
110 ti,davinci-ecc-bits = <4>;
111 ti,davinci-nand-use-bbt;
114 compatible = "fixed-partitions";
115 #address-cells = <1>;
116 #size-cells = <1>;
119 label = "u-boot env";