Lines Matching +full:hs200 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <[email protected]>
11 - Wenbin Mei <[email protected]>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt7988-mmc
25 - mediatek,mt8135-mmc
26 - mediatek,mt8173-mmc
27 - mediatek,mt8183-mmc
28 - mediatek,mt8196-mmc
29 - mediatek,mt8516-mmc
30 - items:
31 - const: mediatek,mt7623-mmc
32 - const: mediatek,mt2701-mmc
33 - items:
34 - enum:
35 - mediatek,mt8186-mmc
36 - mediatek,mt8188-mmc
37 - mediatek,mt8192-mmc
38 - mediatek,mt8195-mmc
39 - mediatek,mt8365-mmc
40 - const: mediatek,mt8183-mmc
45 - description: base register (required).
46 - description: top base register (required for MT8183).
54 clock-names:
60 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
65 interrupt-names:
67 - const: msdc
68 - const: sdio_wakeup
70 pinctrl-names:
72 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
77 - const: default
78 - const: state_uhs
79 - const: state_eint
81 pinctrl-0:
86 pinctrl-1:
91 pinctrl-2:
96 hs400-ds-delay:
99 HS400 DS delay setting.
103 mediatek,hs200-cmd-int-delay:
106 HS200 command internal delay setting.
112 mediatek,hs400-cmd-int-delay:
115 HS400 command internal delay setting.
121 mediatek,hs400-cmd-resp-sel-rising:
128 mediatek,hs400-ds-dly3:
131 Gear of the third delay line for DS for input data latch in data
140 mediatek,latch-ck:
143 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
146 applied to compatible "mediatek,mt2701-mmc".
150 mediatek,tuning-step:
153 Some SoCs need extend tuning step for better delay value to avoid CRC issue.
162 reset-names:
166 - compatible
167 - reg
168 - interrupts
169 - clocks
170 - clock-names
171 - pinctrl-names
172 - pinctrl-0
173 - pinctrl-1
174 - vmmc-supply
175 - vqmmc-supply
178 - $ref: mmc-controller.yaml#
179 - if:
183 - mediatek,mt2701-mmc
184 - mediatek,mt6779-mmc
185 - mediatek,mt6795-mmc
186 - mediatek,mt7620-mmc
187 - mediatek,mt7622-mmc
188 - mediatek,mt7623-mmc
189 - mediatek,mt8135-mmc
190 - mediatek,mt8173-mmc
191 - mediatek,mt8183-mmc
192 - mediatek,mt8186-mmc
193 - mediatek,mt8188-mmc
194 - mediatek,mt8195-mmc
195 - mediatek,mt8196-mmc
196 - mediatek,mt8516-mmc
202 - description: source clock
203 - description: HCLK which used for host
204 - description: independent source clock gate
205 clock-names:
208 - const: source
209 - const: hclk
210 - const: source_cg
212 - if:
216 const: mediatek,mt2712-mmc
222 - description: source clock
223 - description: HCLK which used for host
224 - description: independent source clock gate
225 - description: bus clock used for internal register access (required for MSDC0/3).
226 clock-names:
229 - const: source
230 - const: hclk
231 - const: source_cg
232 - const: bus_clk
234 - if:
239 - mediatek,mt7986-mmc
240 - mediatek,mt7988-mmc
241 - mediatek,mt8183-mmc
242 - mediatek,mt8196-mmc
252 - if:
257 - mediatek,mt7986-mmc
263 - description: source clock
264 - description: HCLK which used for host
265 - description: independent source clock gate
266 - description: bus clock used for internal register access (required for MSDC0/3).
267 - description: msdc subsys clock gate
268 clock-names:
271 - const: source
272 - const: hclk
273 - const: source_cg
274 - const: bus_clk
275 - const: sys_cg
277 - if:
282 - mediatek,mt7988-mmc
287 - description: source clock
288 - description: HCLK which used for host
289 - description: Advanced eXtensible Interface
290 - description: Advanced High-performance Bus clock
291 clock-names:
293 - const: source
294 - const: hclk
295 - const: axi_cg
296 - const: ahb_cg
298 - if:
302 - mediatek,mt8186-mmc
303 - mediatek,mt8188-mmc
304 - mediatek,mt8195-mmc
309 - description: source clock
310 - description: HCLK which used for host
311 - description: independent source clock gate
312 - description: crypto clock used for data encrypt/decrypt (optional)
313 clock-names:
315 - const: source
316 - const: hclk
317 - const: source_cg
318 - const: crypto
320 - if:
324 const: mediatek,mt8192-mmc
329 - description: source clock
330 - description: HCLK which used for host
331 - description: independent source clock gate
332 - description: msdc subsys clock gate
333 - description: peripheral bus clock gate
334 - description: AXI bus clock gate
335 - description: AHB bus clock gate
336 clock-names:
338 - const: source
339 - const: hclk
340 - const: source_cg
341 - const: sys_cg
342 - const: pclk_cg
343 - const: axi_cg
344 - const: ahb_cg
349 - |
350 #include <dt-bindings/interrupt-controller/irq.h>
351 #include <dt-bindings/interrupt-controller/arm-gic.h>
352 #include <dt-bindings/clock/mt8173-clk.h>
354 compatible = "mediatek,mt8173-mmc";
357 vmmc-supply = <&mt6397_vemc_3v3_reg>;
358 vqmmc-supply = <&mt6397_vio18_reg>;
361 clock-names = "source", "hclk";
362 pinctrl-names = "default", "state_uhs";
363 pinctrl-0 = <&mmc0_pins_default>;
364 pinctrl-1 = <&mmc0_pins_uhs>;
365 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
366 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
367 hs400-ds-delay = <0x14015>;
368 mediatek,hs200-cmd-int-delay = <26>;
369 mediatek,hs400-cmd-int-delay = <14>;
370 mediatek,hs400-cmd-resp-sel-rising;
374 compatible = "mediatek,mt8173-mmc";
376 clock-names = "source", "hclk";
379 interrupt-names = "msdc", "sdio_wakeup";
380 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
382 pinctrl-names = "default", "state_uhs", "state_eint";
383 pinctrl-0 = <&mmc2_pins_default>;
384 pinctrl-1 = <&mmc2_pins_uhs>;
385 pinctrl-2 = <&mmc2_pins_eint>;
386 bus-width = <4>;
387 max-frequency = <200000000>;
388 cap-sd-highspeed;
389 sd-uhs-sdr104;
390 keep-power-in-suspend;
391 wakeup-source;
392 cap-sdio-irq;
393 no-mmc;
394 no-sd;
395 non-removable;
396 vmmc-supply = <&sdio_fixed_3v3>;
397 vqmmc-supply = <&mt6397_vgp3_reg>;
398 mmc-pwrseq = <&wifi_pwrseq>;