Lines Matching +full:mode +full:- +full:flag
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <[email protected]>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
30 $ref: /schemas/types.yaml#/definitions/flag
34 cd-gpios:
39 non-removable:
40 $ref: /schemas/types.yaml#/definitions/flag
42 Non-removable slot (like eMMC); assume always present.
48 # low." Therefore, using the "cd-inverted" property means, that the
50 # inserted. Similar logic applies to the "wp-inverted" property.
53 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
55 # using *-inverted properties. GPIO polarity can also be specified
56 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
59 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
60 # respective *-inverted property property results in a
61 # double-inversion and actually means the "normal" line polarity is
63 wp-inverted:
64 $ref: /schemas/types.yaml#/definitions/flag
68 cd-inverted:
69 $ref: /schemas/types.yaml#/definitions/flag
75 bus-width:
82 max-frequency:
85 - for eMMC, the maximum supported frequency is 200MHz,
86 - for SD/SDIO cards the SDR104 mode has a max supported
88 - some mmc host controllers do support a max frequency upto
96 disable-wp:
97 $ref: /schemas/types.yaml#/definitions/flag
99 When set, no physical write-protect line is present. This
101 dedicated write-protect detection logic. If a GPIO is always used
102 for the write-protect detection logic, it is sufficient to not
103 specify the wp-gpios property in the absence of a write-protect
106 wp-gpios:
109 GPIO to use for the write-protect detection.
111 cd-debounce-delay-ms:
116 no-1-8-v:
117 $ref: /schemas/types.yaml#/definitions/flag
122 cap-sd-highspeed:
123 $ref: /schemas/types.yaml#/definitions/flag
125 SD high-speed timing is supported.
127 cap-mmc-highspeed:
128 $ref: /schemas/types.yaml#/definitions/flag
130 MMC high-speed timing is supported.
132 sd-uhs-sdr12:
133 $ref: /schemas/types.yaml#/definitions/flag
137 sd-uhs-sdr25:
138 $ref: /schemas/types.yaml#/definitions/flag
142 sd-uhs-sdr50:
143 $ref: /schemas/types.yaml#/definitions/flag
147 sd-uhs-sdr104:
148 $ref: /schemas/types.yaml#/definitions/flag
152 sd-uhs-ddr50:
153 $ref: /schemas/types.yaml#/definitions/flag
157 cap-power-off-card:
158 $ref: /schemas/types.yaml#/definitions/flag
162 cap-mmc-hw-reset:
163 $ref: /schemas/types.yaml#/definitions/flag
167 cap-sdio-irq:
168 $ref: /schemas/types.yaml#/definitions/flag
172 full-pwr-cycle:
173 $ref: /schemas/types.yaml#/definitions/flag
177 full-pwr-cycle-in-suspend:
178 $ref: /schemas/types.yaml#/definitions/flag
182 mmc-ddr-1_2v:
183 $ref: /schemas/types.yaml#/definitions/flag
185 eMMC high-speed DDR mode (1.2V I/O) is supported.
187 mmc-ddr-1_8v:
188 $ref: /schemas/types.yaml#/definitions/flag
190 eMMC high-speed DDR mode (1.8V I/O) is supported.
192 mmc-ddr-3_3v:
193 $ref: /schemas/types.yaml#/definitions/flag
195 eMMC high-speed DDR mode (3.3V I/O) is supported.
197 mmc-hs200-1_2v:
198 $ref: /schemas/types.yaml#/definitions/flag
200 eMMC HS200 mode (1.2V I/O) is supported.
202 mmc-hs200-1_8v:
203 $ref: /schemas/types.yaml#/definitions/flag
205 eMMC HS200 mode (1.8V I/O) is supported.
207 mmc-hs400-1_2v:
208 $ref: /schemas/types.yaml#/definitions/flag
210 eMMC HS400 mode (1.2V I/O) is supported.
212 mmc-hs400-1_8v:
213 $ref: /schemas/types.yaml#/definitions/flag
215 eMMC HS400 mode (1.8V I/O) is supported.
217 mmc-hs400-enhanced-strobe:
218 $ref: /schemas/types.yaml#/definitions/flag
220 eMMC HS400 enhanced strobe mode is supported
222 no-mmc-hs400:
223 $ref: /schemas/types.yaml#/definitions/flag
235 no-sdio:
236 $ref: /schemas/types.yaml#/definitions/flag
241 no-sd:
242 $ref: /schemas/types.yaml#/definitions/flag
246 no-mmc:
247 $ref: /schemas/types.yaml#/definitions/flag
252 fixed-emmc-driver-type:
254 For non-removable eMMC, enforce this driver type. The value is
261 post-power-on-delay-ms:
263 It was invented for MMC pwrseq-simple which could be referred to
264 mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
266 regardless of whether pwrseq-simple is used. Default to 10ms if
270 supports-cqe:
271 $ref: /schemas/types.yaml#/definitions/flag
276 disable-cqe-dcmd:
277 $ref: /schemas/types.yaml#/definitions/flag
283 keep-power-in-suspend:
284 $ref: /schemas/types.yaml#/definitions/flag
288 wakeup-source:
289 $ref: /schemas/types.yaml#/definitions/flag
293 vmmc-supply:
297 vqmmc-supply:
301 be modeled as a "regulator-fixed" with a GPIO line for
304 mmc-pwrseq:
307 System-on-Chip designs may specify a specific MMC power
312 "^.*@[0-9]+$":
330 - minimum: 0
338 - reg
340 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
341 $ref: /schemas/types.yaml#/definitions/uint32-array
350 controller while switching to particular speed mode. These values
354 cd-debounce-delay-ms: [ cd-gpios ]
355 fixed-emmc-driver-type: [ non-removable ]