Lines Matching +full:input +full:- +full:value
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <[email protected]>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - socionext,uniphier-sd4hc
20 - const: cdns,sd4hc
35 # PHY DLL input delays:
40 cdns,phy-input-delay-sd-highspeed:
41 description: Value of the delay in the input path for SD high-speed timing
46 cdns,phy-input-delay-legacy:
47 description: Value of the delay in the input path for legacy timing
52 cdns,phy-input-delay-sd-uhs-sdr12:
53 description: Value of the delay in the input path for SD UHS SDR12 timing
58 cdns,phy-input-delay-sd-uhs-sdr25:
59 description: Value of the delay in the input path for SD UHS SDR25 timing
64 cdns,phy-input-delay-sd-uhs-sdr50:
65 description: Value of the delay in the input path for SD UHS SDR50 timing
70 cdns,phy-input-delay-sd-uhs-ddr50:
71 description: Value of the delay in the input path for SD UHS DDR50 timing
76 cdns,phy-input-delay-mmc-highspeed:
77 description: Value of the delay in the input path for MMC high-speed timing
82 cdns,phy-input-delay-mmc-ddr:
83 description: Value of the delay in the input path for eMMC high-speed DDR timing
87 # The approximate delay value will be
88 # (<delay property value>/128)*sdmclk_clock_period.
93 cdns,phy-dll-delay-sdclk:
95 Value of the delay introduced on the sdclk output for all modes except
101 cdns,phy-dll-delay-sdclk-hsmmc:
103 Value of the delay introduced on the sdclk output for HS200, HS400 and
109 cdns,phy-dll-delay-strobe:
111 Value of the delay introduced on the dat_strobe input used in
118 - compatible
119 - reg
120 - interrupts
121 - clocks
124 - $ref: sdhci-common.yaml
125 - if:
129 const: amd,pensando-elba-sd4hc
134 - description: Host controller registers
135 - description: Elba byte-lane enable register for writes
137 - resets
146 - |
148 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
152 bus-width = <8>;
153 mmc-ddr-1_8v;
154 mmc-hs200-1_8v;
155 mmc-hs400-1_8v;
156 cdns,phy-dll-delay-sdclk = <0>;