Lines Matching +full:fpga +full:- +full:qixis
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <[email protected]>
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
32 "#size-cells":
49 little-endian:
52 If this property is absent, the big-endian mode will be in use as default
61 "^nand@[a-f0-9]+(,[a-f0-9]+)+$":
65 const: fsl,ifc-nand
70 "#address-cells":
73 "#size-cells":
77 "^partition@[0-9a-f]+":
82 - compatible
83 - reg
87 "(flash|fpga|board-control|cpld)@[a-f0-9]+(,[a-f0-9]+)+$":
90 - $ref: /schemas/board/fsl,fpga-qixis.yaml#
91 - $ref: /schemas/mtd/mtd-physmap.yaml#
95 - compatible
96 - reg
97 - interrupts
102 - |
104 #address-cells = <2>;
105 #size-cells = <2>;
107 memory-controller@ffe1e000 {
109 #address-cells = <2>;
110 #size-cells = <1>;
113 little-endian;
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "cfi-flash";
125 bank-width = <2>;
126 device-width = <1>;