Lines Matching +full:mt8173 +full:- +full:power +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yunfei Dong <[email protected]>
19 - mediatek,mt8173-vcodec-dec
20 - mediatek,mt8183-vcodec-dec
26 reg-names:
28 - const: misc
29 - const: ld
30 - const: top
31 - const: cm
32 - const: ad
33 - const: av
34 - const: pp
35 - const: hwd
36 - const: hwq
37 - const: hwb
38 - const: hwg
47 clock-names:
51 assigned-clocks: true
53 assigned-clock-parents: true
55 assigned-clock-rates: true
57 power-domains:
82 - compatible
83 - reg
84 - interrupts
85 - clocks
86 - clock-names
87 - iommus
88 - mediatek,vdecsys
91 - if:
96 - mediatek,mt8183-vcodec-dec
100 - mediatek,scp
107 clock-names:
109 - const: vdec
111 - if:
116 - mediatek,mt8173-vcodec-dec
120 - mediatek,vpu
127 clock-names:
129 - const: vcodecpll
130 - const: univpll_d2
131 - const: clk_cci400_sel
132 - const: vdec_sel
133 - const: vdecpll
134 - const: vencpll
135 - const: venc_lt_sel
136 - const: vdec_bus_clk_src
141 - |
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
143 #include <dt-bindings/clock/mt8173-clk.h>
144 #include <dt-bindings/memory/mt8173-larb-port.h>
145 #include <dt-bindings/interrupt-controller/irq.h>
146 #include <dt-bindings/power/mt8173-power.h>
149 compatible = "mediatek,mt8173-vcodec-dec";
172 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
181 clock-names = "vcodecpll",
189 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
194 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
197 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;