Lines Matching +full:inter +full:- +full:processor
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Inter-processor communication (IPC) mailbox controller
10 - Valentina Fernandez <[email protected]>
13 The Microchip Inter-processor Communication (IPC) facilitates
20 - description:
22 mode (s-mode). This SBI interface is compatible with the Mi-V
23 Inter-hart Communication (IHC) IP.
24 const: microchip,sbi-ipc
26 - description:
28 (m-mode), this compatible string is for the MIV_IHC Soft-IP.
29 const: microchip,miv-ihc-rtl-v2
38 interrupt-names:
43 - hart-0
44 - hart-1
45 - hart-2
46 - hart-3
47 - hart-4
48 - hart-5
50 "#mbox-cells":
52 For "microchip,sbi-ipc", the cell represents the global "logical"
55 For "microchip,miv-ihc-rtl-v2", the cell represents the physical
59 microchip,ihc-chan-disabled-mask:
61 Represents the enable/disable state of the bi-directional IHC
62 channels within the MIV-IHC IP configuration.
77 - compatible
78 - interrupts
79 - interrupt-names
80 - "#mbox-cells"
83 - if:
87 const: microchip,sbi-ipc
93 The 'microchip,sbi-ipc' operates in a programming model
94 that does not require memory-mapped I/O (MMIO) registers
95 since it uses SBI ecalls provided by the m-mode/firmware
97 microchip,ihc-chan-disabled-mask: false
100 - reg
101 - microchip,ihc-chan-disabled-mask
106 - |
108 compatible = "microchip,sbi-ipc";
109 interrupt-parent = <&plic>;
111 interrupt-names = "hart-1", "hart-2", "hart-3";
112 #mbox-cells = <1>;
114 - |
116 compatible = "microchip,miv-ihc-rtl-v2";
117 microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
119 interrupt-parent = <&plic>;
121 interrupt-names = "hart-1", "hart-2", "hart-3";
122 #mbox-cells = <1>;