Lines Matching +full:pci +full:- +full:iommu
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <[email protected]>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
24 For information on assigning RISC-V IOMMU to its peripheral devices,
25 see generic IOMMU bindings.
28 # For PCIe IOMMU hardware compatible property should contain the vendor
29 # and device ID according to the PCI Bus Binding specification.
30 # Since PCI provides built-in identification methods, compatible is not
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
35 - items:
36 - enum:
37 - qemu,riscv-iommu
38 - const: riscv,iommu
39 - items:
40 - enum:
41 - pci1efd,edf1
42 - const: riscv,pci-iommu
47 For non-PCI devices this represents base address and size of for the
48 IOMMU memory mapped registers interface.
49 For PCI IOMMU hardware implementation this should represent an address
50 of the IOMMU, as defined in the PCI Bus Binding reference.
52 '#iommu-cells':
56 IOMMU.
62 Wired interrupt vectors available for RISC-V IOMMU to notify the
63 RISC-V HARTS. The cause to interrupt vector is software defined
64 using IVEC IOMMU register.
66 msi-parent: true
68 power-domains:
72 - compatible
73 - reg
74 - '#iommu-cells'
79 - |+
80 /* Example 1 (IOMMU device with wired interrupts) */
81 #include <dt-bindings/interrupt-controller/irq.h>
83 iommu1: iommu@1bccd000 {
84 compatible = "qemu,riscv-iommu", "riscv,iommu";
86 interrupt-parent = <&aplic_smode>;
91 #iommu-cells = <1>;
94 /* Device with two IOMMU device IDs, 0 and 7 */
99 - |+
100 /* Example 2 (IOMMU device with shared wired interrupt) */
101 #include <dt-bindings/interrupt-controller/irq.h>
103 iommu2: iommu@1bccd000 {
104 compatible = "qemu,riscv-iommu", "riscv,iommu";
106 interrupt-parent = <&aplic_smode>;
108 #iommu-cells = <1>;
111 - |+
112 /* Example 3 (IOMMU device with MSIs) */
113 iommu3: iommu@1bcdd000 {
114 compatible = "qemu,riscv-iommu", "riscv,iommu";
116 msi-parent = <&imsics_smode>;
117 #iommu-cells = <1>;
120 - |+
121 /* Example 4 (IOMMU PCIe device with MSIs) */
123 #address-cells = <2>;
124 #size-cells = <2>;
127 device_type = "pci";
128 #address-cells = <3>;
129 #size-cells = <2>;
134 * The IOMMU manages all functions in this PCI domain except
137 iommu-map = <0x0 &iommu0 0x0 0x8>,
140 /* The IOMMU programming interface uses slot 00:01.0 */
141 iommu0: iommu@1,0 {
142 compatible = "pci1efd,edf1", "riscv,pci-iommu";
144 #iommu-cells = <1>;