Lines Matching +full:external +full:- +full:memory +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40 contains a specific memory layout, which is documented in chapter 8 of the
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44 T-HEAD PLIC implementation requires setting a delegation bit to allow access
45 from S-mode. So add thead,c900-plic to distinguish them.
48 - Paul Walmsley <[email protected]>
49 - Palmer Dabbelt <[email protected]>
54 - items:
55 - enum:
56 - renesas,r9a07g043-plic
57 - const: andestech,nceplic100
58 - items:
59 - enum:
60 - canaan,k210-plic
61 - sifive,fu540-c000-plic
62 - spacemit,k1-plic
63 - starfive,jh7100-plic
64 - starfive,jh7110-plic
65 - const: sifive,plic-1.0.0
66 - items:
67 - enum:
68 - allwinner,sun20i-d1-plic
69 - sophgo,cv1800b-plic
70 - sophgo,cv1812h-plic
71 - sophgo,sg2002-plic
72 - sophgo,sg2042-plic
73 - thead,th1520-plic
74 - const: thead,c900-plic
75 - items:
76 - const: sifive,plic-1.0.0
77 - const: riscv,plic0
84 '#address-cells':
87 '#interrupt-cells': true
89 interrupt-controller: true
91 interrupts-extended:
95 Specifies which contexts are connected to the PLIC, with "-1" specifying
97 riscv,cpu-intc node, which has a riscv node as parent.
102 Specifies how many external interrupts are supported by this controller.
106 power-domains: true
111 - compatible
112 - '#address-cells'
113 - '#interrupt-cells'
114 - interrupt-controller
115 - reg
116 - interrupts-extended
117 - riscv,ndev
120 - if:
125 - andestech,nceplic100
126 - thead,c900-plic
130 '#interrupt-cells':
135 '#interrupt-cells':
138 - if:
142 const: renesas,r9a07g043-plic
149 power-domains:
156 - clocks
157 - power-domains
158 - resets
163 - |
164 plic: interrupt-controller@c000000 {
165 #address-cells = <0>;
166 #interrupt-cells = <1>;
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
168 interrupt-controller;
169 interrupts-extended = <&cpu0_intc 11>,