Lines Matching +full:ia32 +full:- +full:3 +full:a

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Rahul Tanwar <[email protected]>
13   Intel's Advanced Programmable Interrupt Controller (APIC) is a
14   family of interrupt controllers. The APIC is a split
15   architecture design, with a local component (LAPIC) integrated
28   [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
32     const: intel,ce4100-lapic
37   interrupt-controller: true
39   '#interrupt-cells':
42   intel,virtual-wire-mode:
43     description: Intel defines a few possible interrupt delivery
46       PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
47       Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
56   - compatible
57   - reg
58   - interrupt-controller
59   - '#interrupt-cells'
64   - |
65     lapic0: interrupt-controller@fee00000 {
66         compatible = "intel,ce4100-lapic";
68         interrupt-controller;
69         #interrupt-cells = <2>;
70         intel,virtual-wire-mode;